72V2113L7-5BC IDT, 72V2113L7-5BC Datasheet
72V2113L7-5BC
Specifications of 72V2113L7-5BC
Related parts for 72V2113L7-5BC
72V2113L7-5BC Summary of contents
Page 1
... SCAN) * TDO IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. ...
Page 2
... DESCRIPTION: The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improve- ments over previous SuperSync FIFOs, including the following: • ...
Page 3
... Each FIFO has a data input port (D ) and a data output port (Q n which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface ...
Page 4
... During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory ...
Page 5
... Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. ...
Page 6
... OW Output Width I This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbe config- ured with a x18 bus width HIGH, the read port will bus width. PAE PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset ...
Page 7
... Asynchronous I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW Read Port will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. ASYW (1) Asynchronous I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW Write Port will select Asynchronous operation ...
Page 8
... V V IH, OUT CC. 4. Tested with outputs open (I = 0). OUT 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. For x 18 bus widths, typical 0.002*C CC1 S for x 9 bus widths, typical 0.775*f + 0.002*C CC1 S These equations are valid under the following conditions ...
Page 9
... TM NARROW BUS FIFO (1) = 3.3V ± 0.15V -40°C to +85°C; JEDEC JESD8-A compliant Commercial Com’l & Ind’l (2) BGA & TQFP BGA & TQFP IDT72V2103L6 IDT72V2103L7-5 IDT72V2113L6 IDT72V2113L7-5 Min. Max. Min. Max. — 166 — 133.3 ( — ...
Page 10
... ASYNCHRONOUS TIMING = 3.3V ± 0.15V -40°C to +85°C; JEDEC JESD8-A compliant IDT72V2103L6 IDT72V2113L6 Min. 0.6 4.5 4.5 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Commercial Com’l & Ind’l IDT72V2103L7-5 IDT72V2113L7-5 Max. Min. Max. Unit — 100 — 83 MHz 8 0 — 12 — ...
Page 11
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for t = 10ns ...
Page 12
... If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once (D words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D the 65,537th word for the IDT72V2103 and 131,073rd word for the IDT72V2113 ...
Page 13
... PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V2103/ 72V2113 has internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also be programmed into the FIFO in one of two ways ...
Page 14
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE ≠ IDT72V2103 x18 Number of (n+1) to 65,536 ...
Page 15
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 1st Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER 2nd Parallel Offset Write/Read Cycle D/Q8 EMPTY OFFSET REGISTER 16 15 ...
Page 16
... NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Programmable Flag Offset Programming Sequence (Continued) TM NARROW BUS FIFO ...
Page 17
... The contents of the offset registers can be read on the Q pins when LD is set LOW and REN is set LOW. If the FIFO is configured for an , PAE will be valid input bus width and output bus width both set to x9, then the total number of read PAF plus t ...
Page 18
... IDT72V2113. In FWFT mode, if x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW ...
Page 19
... REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup ...
Page 20
... LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + t after the valid RCLK cycle. SKEW WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. If Asynchronous operation of the Read port has been selected, then WEN must be held active, (tied LOW). READ STROBE & READ CLOCK (RD/RCLK) If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK ...
Page 21
... IR goes HIGH, inhibiting further write operations reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113 ...
Page 22
... HF will go LOW after (D writes to the FIFO. If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode reads are performed after reset (MRS or PRS), HF will go LOW after (D-1 writes to the FIFO ...
Page 23
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT ...
Page 24
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 MRS t RSS REN t RSS WEN t RSS FWFT/SI t RSS LD t RSS ASYW, ASYR t RSS FSEL0, FSEL1 t RSS OW RSS BE t RSS ...
Page 25
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 PRS t RSS REN t RSS WEN t RSS RT t RSS SEN EF/OR FF/IR PAE PAF NARROW BUS FIFO TM NARROW BUS FIFO ...
Page 26
... WCLK and the rising edge of RCLK is less than HIGH. 3. First data word latency 1 SKEW1 RCLK REF Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) TM NARROW BUS FIFO TM NARROW BUS FIFO t CLK t t CLKH ...
Page 27
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 NARROW BUS FIFO TM NARROW BUS FIFO 27 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES JUNE 1, 2010 ...
Page 28
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 NARROW BUS FIFO TM NARROW BUS FIFO 28 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES JUNE 1, 2010 ...
Page 29
... If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked. ...
Page 30
... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113 LOW 4 ...
Page 31
... If x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked. ...
Page 32
... No more than words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113 LOW 4 ...
Page 33
... PAF offset . maximum FIFO depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. ...
Page 34
... D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode: if x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the DT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. ...
Page 35
... Input and x9 Output bus Widths are selected 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113 FWFT mode maximum FIFO depth. If x18 Input or x18 Output bus Width is selected 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. ...
Page 36
... Last Word EF t SKEW WR t CYH t CYC NOTE LOW and WEN = LOW. Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode) TM NARROW BUS FIFO TM NARROW BUS FIFO t t ENS ENH FFA t CYC 2 t REF ...
Page 37
... FF t SKEW t CYL Last Word W X NOTES LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) WCLK t t ENS ENH WEN EFA ...
Page 38
... Last Word in O/P Register t RPE t EFA EF NOTES LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode CYC t t CYH CYL ...
Page 39
... Use an AND gate in IDT Standard mode gate in FWFT mode not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. For the x18 Input or x18 Output bus Width: 131,072 x 36 and 262,144 x 36 ...
Page 40
... DATA IN Dn For the x18 Input or x18 Output bus Width: 262,144 x 18 and 524,288 x 18 For both x9 Input and x9 Output bus Widths: 524,288 x 9 and 1,048,576 x 9 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V2103 can easily be adapted to applications requiring depths greater than 131,072 when the x18 Input or x18 Output bus Width is selected and 262,144 for the IDT72V2113 ...
Page 41
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 JTCKR t JTCKF t JTCKL TCK TDI/ TMS TDO t JRSR TRST (1) t JRST NOTE: 1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. ...
Page 42
... Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V2103/72V2113 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. TDO T ...
Page 43
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 Input = TMS NOTE: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. Refer to the IEEE Standard Test Access Port Specification (IEEE Std. ...
Page 44
... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V2103/72V2113, the Part Number field contains the following ...
Page 45
... IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9 HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO ...
Page 46
... Com‘l & Ind’l, BGA & TQFP Com‘l & Ind’l, TQFP Only Speed in Nanoseconds Commercial, TQFP Only Low Power 131,072 x 18/262,144 x 9 ⎯ 3.3V SuperSync II™ FIFO 262,144 x 18/524,288 x 9 ⎯ 3.3V SuperSync II™ FIFO for Tech Support: 408-360-1753 email: FIFOhelp@idt.com ) CLK 6119 drw37 ...