XRT91L32ES Exar, XRT91L32ES Datasheet - Page 13

• Manufacturer Part Number: XRT91L32ES
• Description: LIN Transceivers SONET SDH 8 bit TRANCEIVER
• Manufacturer: Exar

Specifications of XRT91L32ES

• Product Category: LIN Transceivers
• Rohs: yes

xr
REV. 1.0.3
The XRT91L32 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high-
speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps
(STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622.08 Mbps or
155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-
serialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte
boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to
provide the front end component of SONET equipment, which includes primarily serial transmit and receive
functions.
Functionality of the transceiver can be configured by using the appropriate signal level on the STS-12/STS-3
pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin
Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High."
Therefore, the following sections describe the functionality rather than how each function is controlled. Hence,
the hardware Pin and the Register Bit Descriptions focus on device configuration.
The XRT91L32 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP/N
or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed
clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator
which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the
necessary accuracy required for SONET systems. The reference clock can be provided with one of two
frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L32 are listed in
Table 1.
Due to different operating modes and data logic paths through the device, there is an associated latency from
data ingress to data egress. Table 2 specifies the data latency for a typical path.
Serial Remote Loopback MSB at RXIP/N to MSB at TXOP/N
1.0 FUNCTIONAL DESCRIPTION
1.1
1.2
1.3
CMUFREQSEL
O
M
Thru-mode
PERATION
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
Clock Input Reference for Clock Multiplier (Synthesizer) Unit
Data Latency
ODE
0
0
1
1
O
T
ABLE
F
1: CMU R
MSB at RXIP/N to data on RXDO[7:0]
STS12/STS3
T
EFERENCE
ABLE
0
1
0
1
2: D
D
ATA
ATA INGRESS TO DATA EGRESS LATENCY
F
REQUENCY
REFCLKP/N
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
P
ATH
REFERENCE FREQUENCY
O
11
77.76 MHz
77.76 MHz
19.44 MHz
19.44 MHz
PTIONS
OR
TTLREFCLK
(D
IFFERENTIAL OR
Recoved RXIP/N Clock
Recoved RXIP/N Clock
C
LOCK
R
EFERENCE
S
INGLE
STS-12/STM-4
STS-12/STM-4
STS-3/STM-1
STS-3/STM-1
155.52 Mbps
622.08 Mbps
155.52 Mbps
622.08 Mbps
D
-E
ATA
R
NDED
ANGE
R
)
ATE
C
25 to 35
2 to 4
YCLES
O
XRT91L32
F
C
LOCK