XRT91L32ES Exar, XRT91L32ES Datasheet
XRT91L32ES
Specifications of XRT91L32ES
Related parts for XRT91L32ES
XRT91L32ES Summary of contents
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... STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER PISO Re-Timer (Parallel Input Serial Output) Div by 8 CMU RLOOPS DLOOP SIPO (Serial Input CDR Parallel Output) Control Block • (510) 668-7000 XRT91L32 TXOP/N ALOOP RXIP/N XRXCLKIP/N Clock Control • • FAX (510) 668-7017 www.exar.com REV. 1.0.3 ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1 155.52 Mbps Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit ...
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REV. 1.0 100 QFP P IGURE RLOOPS VDD3.3 ALOOP RESET LOOPTIME CMUFREQSEL VDD_PECL VDD_PECL DLOSDIS XRXCLKIP XRXCLKIN VDD_PECL CDRDIS VDD3.3 REFCLKP REFCLKN P N ART UMBER XRT91L32IQ-F STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER O XRT91L32 ( ...
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XRT91L32 REV. 1.0.3 GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ........................................................................................................................................... XRT91L32 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF ......................................................................................................................................................2 FEATURES F 2. 100 QFP P O IGURE THE ORDERING INFORMATION..................................................................................................................... ............................................................................................................ ABLE OF ONTENTS ...
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 14 IGURE OOP IMING ODE SING 3.6 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... IGURE RANSMIT ERIAL UTPUT 4.0 DIAGNOSTIC FEATURES ................................................................................................................... 26 4.1 SERIAL ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTIONS L32 HARDWARE CONTROL N L AME EVEL RESET LVTTL STS12/STS3 LVTTL CMUFREQSEL LVTTL T P YPE Remote Serial Loopback Active "High." When this pin is pulled "High" , the ...
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REV. 1.0 AME EVEL CDRREFSEL LVTTL LOOPTIME LVTTL CDRDIS LVTTL RLOOPS LVTTL NC No Connect STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER P YPE Clock and Data Recover Unit Reference Frequency Select Selects the Clock ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER AME EVEL ALOOP LVTTL DLOOP LVTTL TRANSMITTER SECTION AME EVEL TXDI0 LVTTL TXDI1 TXDI2 TXDI3 TXDI4 TXDI5 TXDI6 TXDI7 TXOP LVPECL Diff TXON P YPE ...
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REV. 1.0.3 TRANSMITTER SECTION N L AME EVEL TXPCLK_O LVTTL REFCLKP LVPECL Diff REFCLKN TTLREFCLK LVTTL STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER T P YPE Transmit Parallel Clock Output (77.76/19.44 MHz) Transmit Parallel Clock Output Operation This ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER RECEIVER SECTION AME EVEL RXDO0 LVTTL RXDO1 RXDO2 RXDO3 RXDO4 RXDO5 RXDO6 RXDO7 RXIP Diff LVPECL RXIN XRXCLKIP Diff LVPECL XRXCLKIN RXPCLKO LVTTL CDRAUX- LVTTL REFCLK OOF LVTTL FRAMEPULSE LVTTL P ...
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REV. 1.0 AME EVEL CAP1P Analog CAP2P CAP1N Analog CAP2N DLOSDIS LVTTL LOSEXT SE-LVPECL POWER AND GROUND N T AME YPE VDD3.3 PWR 2,28,31,49,54, 58,76,99,81 AVDD3.3_TX PWR AVDD3.3_RX PWR 67,,68,69 VDD_LVPECL PWR 9,15,21 AGND_TX PWR 59,60 ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER N T AME YPE AGND_RX PWR 70,71 GND GND 12,18,34,37,40,43,46,55, 72,75,84,87, Receiver Analog Ground for 3.3V Analog Power Supplies It is recommended that all ground pins of this device be tied together. ...
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REV. 1.0.3 1.0 FUNCTIONAL DESCRIPTION The XRT91L32 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high- speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps (STS-12/STM-4) or ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.0 RECEIVE SECTION The receive section of XRT91L32 include the inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero ...
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REV. 1.0.2 2.2 Recieve Serial Data Input Timing The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing specifications below IGURE ECEIVE IGH PEED ERIAL XRXCLKIP XRXCLKIN ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.3 Receive Clock and Data Recovery The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL receiver and generates a clock that is the same frequency ...
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REV. 1.0 ABLE N AME REF Reference clock duty cycle DUTY REF Reference clock jitter (rms) with 19.44 MHz reference JIT REF Reference clock jitter (rms) with 77.76 MHz reference JIT REF Reference clock frequency tolerance ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.4 External Receive Loop Filter Capacitors These external loop filter 0.47 F non-polarized capacitors provide the necessary components to achieve the required receiver jitter performance. They must be well isolated to prohibit noise entering ...
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REV. 1.0.2 2.6 SONET Frame Boundary Detection and Byte Alignment Recovery A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1 (0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.8 Receive Parallel Output Interface The 8-bit Single-Ended LVTTL running at 77.76 Mbps (STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) parallel data output of the receive path is used to interface to a SONET Framer/ASIC synchronized ...
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REV. 1.0.2 2.10 Receive Parallel Data Output Timing The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and hold times shown in Figure 10 ,Table 7, and Table 8. Table 9 shows ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER T 9: PECL ABLE S YMBOL t PECL output rise time (20% to 80%) R_PECL t PECL output fall time (80% to 20%) F_PECL t TTL output rise time (10% to 90%) R_TTL t ...
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REV. 1.0.3 3.0 TRANSMIT SECTION The transmit section of the XRT91L32 accepts 8-bit parallel data and converts it to serial Differential LVPECL data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.2 Transmit Parallel Data Input Timing When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 12 and Table 10, Table 11. F 12. ...
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REV. 1.0.3 3.3 Transmit Parallel Input to Serial Output (PISO) The PISO is used to convert 77.76 Mbps or 19.44 Mbps parallel data input to 622.08 Mbps STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 serial data output respectively, which can interface ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER N AME ECLK STS-12/STM-4 Electrical Clock output jitter (rms) with 77.76 MHz reference JIT OCLK Frequency output FREQ OCYC Clock output duty cycle (’1010’ data pattern) DUTY Jitter specification is defined using a 12kHz ...
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REV. 1.0 IGURE OOP IMING ODE SING REFCLKP REFCLKN TTLREFCLK TXDI[7:0] TXPCLK_IO ENB ENB VDD LOOPTIME CDRDIS RXDO[7: RXPCLKO Div by 8 3.6 Transmit Serial Output Control The 622.08 Mbps STS-12/STM-4 ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at ...
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REV. 1.0.3 4.3 Analog Local Loopback Analog Local Loopback (ALOOP) controls a more comprehensive version of digital local loopback in which the point where the transmit data is looped back is moved all the way back to the high-speed ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.5 Eye Diagram The XRT91L32 Eye diagram illustrates the transmit serial output signal integrity and quality. F 20. STS-3/STM IGURE YE IAGRAM F 21. STS-12/STM IGURE YE IAGRAM 28 xr ...
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REV. 1.0.3 4.6 SONET Jitter Requirements SONET equipment jitter requirements are specified for the following three types of jitter. The definitions of each of these types of jitter are given below. SONET equipment jitter requirements are specified for the ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 23. XRT91L32 M IGURE EASURED F 24. XRT91L32 M IGURE EASURED J T 622.08 M ITTER OLERANCE AT BPS J T 155.52 M ITTER OLERANCE AT BPS 30 xr REV. 1.0.3 STS-12/STM-4 STS-3/STM-1 ...
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REV. 1.0.3 4.6.2 Jitter Generation Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The Bellcore and ITU requirement for this type jitter is 0.01UI rms measured with ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Thermal Resistance of QFP Package........ Thermal Resistance of QFP Package........ ESD Protection (HBM)..........................................>2000V ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS S T YMBOL YPE VDD CMOS Digital Power Supply ...
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REV. 1.0.3 LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Conditions 25°C, VDD = 3. unless otherwise specified YMBOL YPE ARAMETER V LVPECL Output High Voltage OH V LVPECL Output Low ...
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XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER P N ART UMBER XRT91L32IQ-F 100-pin Plastic Quad Flat Pack (14.0 x 20.0 x 2.7 mm PACKAGE DIMENSIONS 81 100 A A Seating Plane A 1 SYMBOL ...
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... Made pin 81 VDD only Minor editorial corrections EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...