NB3H83905CDTG ON Semiconductor, NB3H83905CDTG Datasheet - Page 8

• Manufacturer Part Number: NB3H83905CDTG
• Description: Buffers & Line Drivers 1.8V/2.5V/3.3 V BUFFER
• Manufacturer: ON Semiconductor

Specifications of NB3H83905CDTG

• Product Category: Buffers & Line Drivers
• Rohs: yes
• Number Of Input Lines: 1
• Number Of Output Lines: 6
• Polarity: Non-Inverting
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16

Table 7. AC CHARACTERISTICS
V
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
5. Crystal inputs v F
tSKEW
tSKEW
tSKEW
tSKEW
tSKEW
tSKEW
DD
t
FNOISE
DD
t
FNOISE
DD
t
FNOISE
Symbol
EN
EN
EN
tJIT(F)
tJIT(F)
tJIT(F)
See Figures 4 and 7. See APPLICATION INFORMATION; Crystal Input Interface for CL loading.
F
F
F
tr/tf
tr/tf
tr/tf
= 3.135 V to 3.465 V (3.3 V $5%); V
max
= 3.135 V to 3.465 V (3.3 V $5%); V
max
= 2.375 V to 2.625 V (2.5 V $5%); V
max
/ t
/ t
/ t
DIS
DIS
DIS
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
O−O
O−O
O−O
DC
DC
DC
Input Frequency Crystal
Input Frequency Clock (XTAL_IN/CLK)
Delay for Output Enable / Disable Time ENABLEx to BCLKn
Duty Cycle Skew (See Figure 4)
Output to Output Skew Within A Device (same conditions)
Phase−Noise Performance f
RMS Phase Jitter
Output rise and fall times (20%; 80%)
Input Frequency Crystal
Input Frequency Clock (XTAL1)
Delay for Output Enable / Disable Time ENABLEx to BCLKn
Duty Cycle Skew (See Figure 4)
Output to Output Skew Within A Device (same conditions)
Phase−Noise Performance f
RMS Phase Jitter
Output rise and fall times (20%; 80%)
Input Frequency Crystal
Input Frequency Clock (XTAL1)
Delay for Output Enable / Disable Time ENABLEx to BCLKn
Duty Cycle Skew (See Figure 4)
Output to Output Skew Within A Device (same conditions)
Phase−Noise Performance f
RMS Phase Jitter
Output rise and fall times (20%; 80%)
max
. Outputs loaded with 50 W to V
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 12 kHz to 20 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
25 MHz carrier, Integration Range 100 Hz to 1 MHz
(continued)
DDO
DDO
DDO
Characteristic
out
out
out
= 25 MHz
= 25 MHz
= 25 MHz/
= 2.375 V to 2.625 V (2.5 V $5%); GND = 0 V, T
= 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, T
= 1.6 V to 2.0 V (1.8 V $0.2 V); GND = 0 V, T
DDO
http://onsemi.com
/2. CLOCK (LVCMOS levels at XTAL1 input) 50% duty cycle.
100 kHz off Carrier
100 kHz off Carrier
100 kHz off Carrier
100 Hz off Carrier
10 kHz off Carrier
100 Hz off Carrier
10 kHz off Carrier
100 Hz off Carrier
10 kHz off Carrier
8
1 kHz off Carrier
1 kHz off Carrier
1 kHz off Carrier
Min
200
200
200
DC
DC
DC
48
48
47
3
0
A
3
0
A
3
0
= −405C to +855C (Note 5)
= −405C to +855C (Note 5)
A
= −405C to +855C (Note 5)
−129
−145
−147
−157
−129
−145
−147
−157
−129
−145
−147
−157
0.14
0.14
0.18
0.18
0.19
0.19
Typ
50
50
50
Max
100
800
100
900
100
900
40
52
80
40
52
80
40
53
80
4
4
4
dBc/Hz
dBc/Hz
dBc/Hz
Cycles
Cycles
Cycles
Unit
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
%