NB3H83905CDTG ON Semiconductor, NB3H83905CDTG Datasheet
NB3H83905CDTG
Specifications of NB3H83905CDTG
Related parts for NB3H83905CDTG
NB3H83905CDTG Summary of contents
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NB3H83905C 1.8V/2.5V/3.3V Crystal Input to 1:6 LVTTL/LVCMOS Clock Fanout Buffer with OE Description The NB3H83905C is a 1 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by flexible 1 ...
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XTAL_OUT 1 16 ENABLE2 2 15 GND 3 14 BCLK0 DDO BCLK1 6 11 GND 7 10 BCLK2 8 9 SOIC−16/TSSOP−16 Table 1. PIN DESCRIPTION SOIC−16 / TSSOP−16 QFN−20 Name 1 19 XTAL_OUT 2 20 ...
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Table 2. CLOCK ENABLE FUNCTION TABLE Control Inputs ENABLE1 *Defaults HIGH when floating open. BCLK5 BCLK0:4 ENABLE2 ENABLE1 The ENABLEx control inputs will synchronously enable or disable the selected output(s). This control detects the falling edge ...
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Table 5. MAXIMUM RATINGS (Note 2) Symbol Parameter V Positive Power Supply DDx V Input Voltage I T Operating Temperature Range, Industrial A T Storage Temperature Range stg q Thermal Resistance (Junction−to−Ambient) JA Thermal Resistance (Junction−to−Case Thermal ...
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Table 6. DC CHARACTERISTICS Symbol Characteristic 3.135 V to 3.465 V (3.3 V $5%); GND = DDO IDD Core Quiescent Power Supply Current (ENABLEx = LOW) IDDO Output Quiescent Power Supply Current ...
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Table 6. DC CHARACTERISTICS (continued) Symbol Characteristic V = 3.135 V to 3.465 V (3.3 V $5%); V DD IDD Core Quiescent Power Supply Current (ENABLEx = LOW) IDDO Output Quiescent Power Supply Current (ENABLEx = LOW) V Input HIGH ...
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Table 7. AC CHARACTERISTICS Symbol 3.135 V to 3.465 V (3 5%); GND = DDO F Input Frequency Crystal max Input Frequency Clock (XTAL_IN/CLK Delay for Output ...
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Table 7. AC CHARACTERISTICS (continued) Symbol V = 3.135 V to 3.465 V (3.3 V $5%); Input Frequency Crystal max Input Frequency Clock (XTAL_IN/CLK Delay for Output Enable / Disable Time ENABLEx to BCLKn ...
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V BCLKx BCLKy t SKEW O−O V DDO 2 BCLKx BCLKx Figure 4. AC Reference Measurement Figure 5. Typical Phase Noise Plot of the NB3H83905C Operating at 25 MHz V V DDO DDO DDO DDO 2 ...
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Figure 6. Typical Phase Noise Plot of the NB3H83905C Operating at 25 MHz NB3H83905C DUT GND Figure 7. Typical Device Evaluation and Termination Setup − See Table 8 Table 8. TEST SUPPLY SETUP. V DDO CONNECTION INTO ...
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... W pullup resistor to GND at the receiver DD pin, instead source termination resistor, Figure 10. ORDERING INFORMATION Device NB3H83905CDG NB3H83905CDR2G NB3H83905CDTG NB3H83905CDTR2G NB3H83905CMNG NB3H83905CMNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. APPLICATION INFORMATION Unused Input and Output Pins All LVCMOS control pins have internal pull− ...
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... G K −T− SEATING PLANE 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K −B− 0.25 (0.010 ...
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... −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−16 CASE 948F ISSUE É ...
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... PACKAGE OUTLINE b *For additional information on our Pb−Free strategy and soldering 0. details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0.05 C NOTE 3 N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: ...