NB3H83905CDTG ON Semiconductor, NB3H83905CDTG Datasheet - Page 11

• Manufacturer Part Number: NB3H83905CDTG
• Description: Buffers & Line Drivers 1.8V/2.5V/3.3 V BUFFER
• Manufacturer: ON Semiconductor

Specifications of NB3H83905CDTG

• Product Category: Buffers & Line Drivers
• Rohs: yes
• Number Of Input Lines: 1
• Number Of Output Lines: 6
• Polarity: Non-Inverting
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-16

Crystal Input Interface
oscillator interface using a typical parallel resonant crystal.
A parallel crystal with loading capacitance C
would use C1 = 32 pF and C2 = 32 pF as nominal values,
assuming 4 pF of stray cap per line. The frequency accuracy
and duty cycle skew can be fine tuned by adjusting the C1
and C2 values. For example, increasing the C1 and C2
values will reduce the operational frequency. Note R1 is
optional and may be 0 W.
Termination
used by locating a 28 W series resistor at the driver pin as
shown in Figure 9. Alternatively, a Thevenin Parallel
termination may be used by locating a 100 W pullup resistor
to V
pin, instead of an Rs source termination resistor, Figure 10.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ORDERING INFORMATION
NB3H83905CDG
NB3H83905CDR2G
NB3H83905CDTG
NB3H83905CDTR2G
NB3H83905CMNG
NB3H83905CMNTXG
Figure 8 shows the NB3H83905C device crystal
Figure 8. NB3H83905C Crystal Oscillator Interface
NB3H83905C device output series termination may be
32 pF
32 pF
DD
and a 100 W pullup resistor to GND at the receiver
C1
C2
Device
X1 18 pF
Parallel Resonant
Crystal
R1*
* R1 is optional
XTAL_IN/CLK
XTAL_OUT
NB3H83905C
APPLICATION INFORMATION
L
= 18 pF
(Pb*Free)
(Pb*Free)
TSSOP−16
(Pb*Free)
TSSOP−16
(Pb*Free)
(Pb−Free)
Package
SOIC−16
SOIC−16
Pb−Free)
http://onsemi.com
QFN−20
QFN−20
11
Unused Input and Output Pins
pull−downs; additional external resistors are not required
(optionally 1 kW resistors may be used). All unused
LVCMOS outputs can be left floating with no trace attached.
Bypass
both a 10 mF and a 0.1 mF cap from supply pins to GND.
All LVCMOS control pins have internal pull−ups or
The V
BCLKx
BCLKx
Figure 10. Optional Thevenin Termination
DD
and V
Figure 9. Series Termination
DDO
Rseries = 28 W
supply pins should be bypassed with
2500 Units / Tape & Reel
2500 Units / Tape & Reel
3000 / Tape & Reel
R = 100 W
R = 100 W
48 Units / Rail
92 Units / Rail
96 Units /Rail
Shipping
†
LVCMOS
LVCMOS