GLS55VD020-60-C-TQWE-DZ019 Greenliant, GLS55VD020-60-C-TQWE-DZ019 Datasheet - Page 23

• Manufacturer Part Number: GLS55VD020-60-C-TQWE-DZ019
• Description: Flash ATA Media 60MHz 2.7V Commercial
• Manufacturer: Greenliant

Specifications of GLS55VD020-60-C-TQWE-DZ019

• Rohs: yes
• Memory Type: NAND Flash
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100

NAND Controller
GLS55VD020
Word 60-61: Total Sectors Addressable in LBA Mode This field contains the number of sectors addressable for the
Word 63: Multi-word DMA Transfer Mode This field identifies the multi-word DMA transfer modes supported by the
Word 64: Advanced PIO Data Transfer Mode Bits (7:0) is defined as the PIO data and register transfer supported
Word 65: Minimum Multi-word DMA Transfer Cycle Time Per Word This field defines the minimum Multi-word
Word 66: Device Recommended Multi-word DMA Cycle Time This
©2010 Greenliant Systems, Ltd.
The Even Byte value depends on the value set by the Set Multiple command. The Even Byte of this word by
default contains a 00H which indicates that Read/Write Multiple commands are not valid.
NAND Controller in LBA mode only.
NAND Controller and indicates the mode that is currently selected. Only one DMA mode can be selected at
any given time.
Bit
15-11
10
9
8
7-3
2
1
0
field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Any number of bits
may be set to one in this field by the device to indicate the PIO modes the device is capable of supporting. Of
these bits, bits (7:2) are Reserved for future PIO modes.
Bit
0
1
DMA transfer cycle time per word. This field defines, in nanoseconds, the minimum cycle time that the NAND
Controller supports when performing Multi-word DMA transfers on a per word basis. Greenliant’s NAND
Controller supports up to Multi-word DMA Mode-2, so this field is set to 120ns.
recommended Multi-word DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time
per word during a single sector host transfer while performing a multiple sector READ DMA or WRITE DMA
command for any location on the media under nominal conditions. If a host runs at a faster cycle rate by
operating at a cycle time of less than this value, the NAND Controller may negate DMARQ for flow control. The
rate at which DMARQ is negated could result in reduced throughput despite the faster cycle rate. Transfer at
Function
Reserved
Multi-word DMA mode 2 selected
1: Multi-word DMA mode 2 is selected and bits 8 and 9 are cleared to 0
0: Multi-word DMA mode 2 is not selected.
Multi-word DMA mode 1 selected
1: Multi-word DMA mode 1 is selected and 8 and 10 should be cleared to 0.
0: Multi-word DMA mode 1 is not selected.
Multi-word DMA mode 0 selected
1: Multi-word DMA mode 0 is selected and bits 9 and 10 are cleared to 0.
0: Multi-word DMA mode 0 is not selected.
Reserved
Multi-word DMA mode 2 supported
1: Multi-word DMA mode 2 and below are supported and Bits 0 and 1 are set to 1.
Multi-word DMA mode 1 supported
1: Multi-word DMA mode 1 and below are supported.
Multi-word DMA mode 0 supported
1: Multi-word DMA mode 0 is supported.
Function
1: NAND Controller supports PIO Mode-3.
1: NAND Controller supports PIO Mode-4.
23
field
defines
the
NAND
S71355-05-000
Data Sheet
Controller
05/10