GLS55VD020-60-C-TQWE-DZ019 Greenliant, GLS55VD020-60-C-TQWE-DZ019 Datasheet - Page 18

• Manufacturer Part Number: GLS55VD020-60-C-TQWE-DZ019
• Description: Flash ATA Media 60MHz 2.7V Commercial
• Manufacturer: Greenliant

Specifications of GLS55VD020-60-C-TQWE-DZ019

• Rohs: yes
• Memory Type: NAND Flash
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100

Data Sheet
Device Control Register (Write Only) This register is used to control the NAND Controller interrupt request and
to issue a software reset. This register can be written to even if the device is busy. The bits are defined as follows:
Command Register (Write Only) This register contains the command code being sent to the drive. Command
execution begins immediately after this register is written. The executable commands, the command codes, and
the necessary parameters for each command are listed in Table 7.
NAND Controller Command Description
This section defines the software requirements and the format of the commands the host sends to the NAND Controller.
Commands are issued to the NAND Controller by loading the required registers in the command block with the supplied
parameters, and then writing the command code to the Command register. With the exception of commands listed in
Sections -, NAND Controller complies with ATA-6 Specifications.
NAND Controller Command Set
Table 7 summarizes the NAND Controller command set.
TABLE 7: NAND Controller Command Set (1 of 2)
©2010 Greenliant Systems, Ltd.
Command
Check-Power-Mode
Symbol
BUSY
RDY
DWF
DSC
DRQ
CORR
ERR
Symbol
SW Rst
-IEn
D7
X
Function
The busy bit is set when the NAND Controller has access to the command buffer and
registers and the host is locked out from accessing the Command register and buffer. No
other bits in this register are valid when this bit is set to a 1.
RDY indicates whether the device is capable of performing NAND Controller operations.
This bit is cleared at power up and remains cleared until the NAND Controller is ready to
accept a command.
This bit, if set, indicates a write fault has occurred.
This bit is set when the NAND Controller is ready.
The Data-Request bit is set when the NAND Controller requires that information be
transferred either to or from the host through the Data register.
This bit is set when a correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector Read operation.
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error. It is required that
the host retry any media access command (such as Read-Sectors and Write-Sectors)
that end with an error condition.
Function
This bit is set to 1 in order to force the NAND Controller to perform a software Reset
operation. The chip remains in reset until this bit is reset to ‘0.’
0: The Interrupt Enable bit enables interrupts
1: Interrupts from the NAND Controller are disabled
This bit is set to 0 at Power-on and Reset.
D6
X
D5
X
E5H or 98H
D4
X
Code
18
D3
1
FR
-
1
SW Rst
D2
SC
-
2
SN
-IEn
D1
-
3
NAND Controller
CY
-
4
D0
0
S71355-05-000
GLS55VD020
DH
D
8
5
Reset Value
0000 1000b
LBA
-
6
05/10