C8051F964-A-GQ Silicon Labs, C8051F964-A-GQ Datasheet - Page 335

• Manufacturer Part Number: C8051F964-A-GQ
• Description: 8-bit Microcontrollers - MCU 64KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F964-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

26.2. Mapping Data Registers to LCD Pins
The LCD0 data registers are organized as 16 byte-wide special function registers (LCD0Dn), each half-
byte or nibble in these registers controls 1 LCD output pin. There are 32 nibbbles used to control the 32
segment pins.
Each LCD0 segment pin can control 1, 2, 3, or 4 LCD segments depending on the selected mux mode.
The least significant bit of each nibble controls the segment connected to the backplane signal COM0. The
next to least significant bit controls the segment associated with COM1, the next bit controls the segment
associated with COM2, and the most significant bit in the 4-bit nibble controls the segment associated with
COM3.
In static mode, only the least significant bit in each nibble is used and the three remaining bits in each nib-
ble are ignored. In 2-mux mode, only the two least significant bits are used; in 3-mux mode, only the three
least significant bits are used, and in 4-mux mode, each of the 4 bits in the nibble controls one LCD seg-
ment. Bits with a value of 1 turn on the associated segment and bits with a value of 0 turn off the associ-
ated segment.
SFR Definition 26.1. LCD0Dn: LCD0 Data
SFR Page: 0x2
Addresses: LCD0D0 = 0x89, LCD0D1 = 0x8A, LCD0D2 = 0x8B, LCD0D3 = 0x8C,
Name
Reset
Type
7:0
Bit
Bit
8. Set the LCD contrast using the LCD0CNTRST register.
9. Set the desired threshold for the VBAT Supply Monitor.
10. Set the LCD refresh rate using the LCD0DIVH:LCD0DIVL registers.
11. Write a pattern to the LCD0Dn registers.
12. Enable the LCD by setting bit 0 of LCD0MSCN to logic 1 (LCD0MSCN |= 0x01).
LCD0CF Register.
LCD0Dn
LCD0D4 = 0x8D, LCD0D5 = 0x8E, LCD0D6 = 0x91, LCD0D7 = 0x92,
LCD0D8 = 0x93, LCD0D9 = 0x94, LCD0DA = 0x95, LCD0DB = 0x96,
LCD0DC = 0x97, LCD0DD = 0x99, LCD0DE = 0x9A, LCD0DF = 0x9B.
R/W
Name
7
0
LCD Data.
Each nibble controls one LCD pin.
See “Mapping Data Registers to LCD Pins” on page 335 for additonal informatoin.
R/W
6
0
R/W
5
0
Rev. 0.5
R/W
4
0
LCD0Dn
Function
R/W
3
0
R/W
2
0
C8051F96x
R/W
1
0
R/W
0
0
335