MAX1080BCUP+T Maxim Integrated, MAX1080BCUP+T Datasheet - Page 7

• Manufacturer Part Number: MAX1080BCUP+T
• Description: Analog to Digital Converters - ADC 5V 400ksps Low-Power 8Ch Serial 10-Bit
• Manufacturer: Maxim Integrated

Specifications of MAX1080BCUP+T

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 60 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 559 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

8-Channel, Serial 10-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1081
(Figures 1, 2, 6, 7; V
Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
Note 3: Offset nulled.
Note 4: Ground the “on” channel; sine wave is applied to all “off” channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs (CH7–CH0 and COM) is from GND to V
Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is the
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Electrical characteristics are guaranteed from V
Note 10: AIN= midscale. Unipolar mode. MAX1080 tested with 20pF on DOUT, 20pF on SSTRB, and f
Note 11: SCLK = DIN = GND, CS = V
SCLK Period
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
SCLK Rise to DOUT Valid
SCLK Rise to SSTRB Valid
CS Rise to DOUT Disable
CS Rise to SSTRB Disable
CS Fall to DOUT Enable
CS Fall to SSTRB Enable
CS Pulse Width High
been calibrated.
result of production test limitations.
this range, see Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
MAX1081 tested with same loads, f
PARAMETER
300ksps/400ksps, Single-Supply, Low-Power,
DD1
_______________________________________________________________________________________
DD1
= V
= V
DD2
DD2
= +2.7V to +3.6V, T
= V
SYMBOL
DD(MIN)
t
t
t
t
t
t
t
t
t
t
t
t
t
DOH
DOD
CSW
DD1
t
t
CSH
CSO
DOV
DOE
t
t
t
CSS
CS1
STH
STD
STV
STE
CH
DH
CP
CL
DS
.
, COM = GND, unipolar single-ended input mode.
SCLK
C
C
C
C
C
C
C
C
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
= 4.8MHz, 0 to 3V.
A
= T
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
MIN
DD1(MIN)
to T
CONDITIONS
MAX
= V
, unless otherwise noted.)
DD2(MIN)
to V
DD1(MAX)
= V
DD2(MIN)
DD1
MIN
208
100
83
83
45
45
45
45
13
13
13
13
0
0
.
SCLK
. For operations beyond
TYP
= 6.4MHz, 0 to 5V.
20
20
MAX
100
100
85
85
85
85
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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