MAX1080BCUP+T Maxim Integrated, MAX1080BCUP+T Datasheet - Page 11

• Manufacturer Part Number: MAX1080BCUP+T
• Description: Analog to Digital Converters - ADC 5V 400ksps Low-Power 8Ch Serial 10-Bit
• Manufacturer: Maxim Integrated

Specifications of MAX1080BCUP+T

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 400 KSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 60 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 559 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

8-Channel, Serial 10-Bit ADCs with Internal Reference
The MAX1080/MAX1081 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 10-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1080/MAX1081.
The equivalent circuit of Figure 4 shows the MAX1080/
MAX1081s’ input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 1 and 2.
The MAX1080/MAX1081 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
Figure 3. Functional Diagram
REFADJ
SHDN
SCLK
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DIN
CS
REF
12
11
17
18
16
10
1
2
3
5
6
7
8
9
4
REGISTER
ANALOG
INPUT
INPUT
SHIFT
MUX
300ksps/400ksps, Single-Supply, Low-Power,
REFERENCE
+1.22V
______________________________________________________________________________________
CONTROL
LOGIC
T/H
Detailed Description
Pseudo-Differential Input
17k
A ≈
+2.500V
IN
CLOCK
2.05
10 + 2-BIT
SAR ADC
CLOCK
REF
INT
OUT
MAX1080
MAX1081
REGISTER
OUTPUT
SHIFT
20
19
13
14
15
DOUT
SSTRB
V
V
GND
DD1
DD2
sinusoidal signal at IN-, the input voltage is determined
by:
The maximum voltage variation is determined by:
A 2.6Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / f
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
C
sion interval begins with the input multiplexer switching
C
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to V
tion. This action is equivalent to transferring a
12pF
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
Figure 4. Equivalent Input Circuit
HOLD
HOLD
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
*INCLUDES ALL INPUT PARASITICS
max
✕
[(V
from IN+ to IN-. This unbalances node ZERO at
as a sample of the signal at IN+. The conver-
INPUT
MUX
IN
d
GND
C
REF
SWITCH
ν
dt
+ - V
IN
−
*
DD1
=
IN
6pF
ν
(
IN
-)] charge from C
V
HOLD
C
12pF
IN
/2 within the limits of 10-bit resolu-
HOLD
−
CAPACITIVE
−
=
)
(
DAC
2 f
V
π
IN
TRACK
ZERO
R
800Ω
−
≤
IN
)
SCLK
t
sin(2 ft)
1LSB
CONV
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
π
). When a DC refer-
HOLD
V
=
DD1
2 t
/2
COMPARATOR
10
V
to the binary-
REF
CONV
HOLD
. The
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