MAX9322ECY-D Maxim Integrated, MAX9322ECY-D Datasheet - Page 9

• Manufacturer Part Number: MAX9322ECY-D
• Description: Communication ICs - Various LVECL/LVPECL 1
• Manufacturer: Maxim Integrated
• Type: Differential Divide-by-1/Divide-by-2 Clock Driverr

Specifications of MAX9322ECY-D

• Supply Voltage - Max: +/- 3.8 V
• Supply Voltage - Min: +/- 2.375 V
• Supply Current: 66 mA
• Operating Supply Voltage: +/- 2.5 V, +/- 3.3 V
• Supply Type: Analog

The MAX9322 low-skew 1:15 differential clock driver
reproduces or divides one of two differential input
clocks at 15 differential outputs. An input multiplexer
selects from one of two input clocks with input frequen-
cy operation in excess of 1.0GHz. The 15 outputs are
arranged into four banks with 2, 3, 4, and 6 outputs,
respectively. Each output bank is individually program-
mable to provide a divide-by-1 or divide-by-2 frequen-
cy function.
Output levels are referenced to V
LVECL, depending on the level of the V
V
to ground, the outputs are LVPECL. The outputs are
LVECL when V
connected to a negative supply. When interfacing to
differential LVPECL signals, the V
3.8V (V
bution in systems with nominal 2.5V and 3.3V supplies.
When interfacing to differential LVECL, the V
-2.375V to -3.8V (V
The MAX9322 provides four output banks: A, B, C, and
D. Bank A consists of two differential output pairs. Bank
B consists of three differential output pairs. Bank C
consists of four differential output pairs. Bank D con-
sists of six differential output pairs. FSEL_ selects the
output clock frequency for a bank. A low on FSEL_
selects divide-by-1 frequency operation while a high on
FSEL_ selects divide-by-2 operation. CLK_SEL selects
CLK0 or CLK1 as the input signal. A low on CLK_SEL
selects CLK0 while a high selects CLK1.
Master reset (MR) enables all outputs. CLK_SEL and
FSEL_ are asynchronous. Changes to the control inputs
(CLK_SEL, FSEL_) or on power-up cause indeterminate
output states requiring a MR assertion to resynchronize
any divide-by-2 outputs (Figure 4). A low on MR activates
Figure 3. Timing Diagram for MR
CC
connected to a positive supply and V
EE
Control Inputs (FSEL_, CLK_SEL, MR)
= 0), allowing high-performance clock distri-
CC
_______________________________________________________________________________________
CC
is connected to ground and V
= 0).
Detailed Description
LVECL/LVPECL Operation
Divide-by-1/Divide-by-2 Clock Driver
MR
Q_
Q_
CC
CC
and are LVPECL or
range is 2.375V to
CC
LVECL/LVPECL 1:15 Differential
EE
supply. With
EE
connected
range is
EE
is
all outputs for normal operation. A high on MR resets all
outputs to differential low condition. See Table 1.
Differential inputs CLK_ and CLK_ are biased to guar-
antee a known state (differential low) if the inputs are
left open. CLK_ is internally pulled to V
75kΩ resistor. CLK_ is internally pulled to V
V
Single-ended inputs FSEL_, MR, and CLK_SEL are
internally pulled to V
The MAX9322 accepts two differential or single-ended
clock inputs, CLK0/CLK0 and CLK1/CLK1. CLK_SEL
selects between CLK0/CLK0 and CLK1/CLK1. A low on
CLK_SEL selects CLK0/CLK0. A high on CLK_SEL
selects CLK1/CLK1. See Table 1.
Differential CLK_ inputs must be at least V
switch the outputs to the V
in the DC Electrical Characteristics table. The maximum
magnitude of the differential signal applied to the differ-
ential clock input is the lower of (V
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
Specifications for the high and low voltages of a differ-
ential input (V
voltage (V
Table 1. Function Table
*A master reset is required following power-up or changes to
input functions to prevent indeterminant output states.
EE
CLK_SEL
through 75kΩ resistors.
FSEL_
MR*
PIN
t
PD
IHD
- V
IHD
ILD
LOW OR OPEN
and V
Input Termination Resistors
) apply simultaneously.
EE
Divide-by-1
V
V
V
V
V
IH
BB
IL
OH
OL
Active
CLK0
through a 75kΩ resistor.
ILD
Differential Clock Input
OH
) and the differential input
and V
FUNCTION
CC
OL
- V
levels specified
Divide-by-2
EE
EE
BB
HIGH
Reset
CLK1
) and 3.0V.
CC
through a
±95mV to
and to
9