MAX9322ECY-D Maxim Integrated, MAX9322ECY-D Datasheet
MAX9322ECY-D
Specifications of MAX9322ECY-D
Related parts for MAX9322ECY-D
MAX9322ECY-D Summary of contents
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... Propagation Delay ♦ Selectable Divide-by-1 or Divide-by-2 Frequency Outputs ♦ Multiplexed 2:1 Input Function ♦ LVECL Operation from V ♦ LVPECL Operation from V ♦ ESD Protection: > 2kV Human Body Model MAX9322ECY Applications MAX9322ETK* *Future product—contact factory for availability. TOP VIEW V CC ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver ABSOLUTE MAXIMUM RATINGS .............................................................................4. Inputs and Outputs to V ..........................-0. Differential Input Magnitude............Lower of (V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA V Sink/Source Current ...............................................±0.65mA ...
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Divide-by-1/Divide-by-2 Clock Driver DC ELECTRICAL CHARACTERISTICS (continued) (( 2.375V to 3.8V, outputs loaded with 50Ω ± the lower and 3V. Typical values are ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver AC ELECTRICAL CHARACTERISTICS (( 2.375V to 3.8V; outputs loaded with 50Ω ± (20% to 80%); CLK_SEL, FSEL_ = high or low low; V 1V. ...
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Divide-by-1/Divide-by-2 Clock Driver ( 3.3V 1V IHD CC otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE -40 - TEMPERATURE (°C) PROPAGATION ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver PIN NAME TQFP QFN FSELA 4 6 FSELB 5 7 CLK0 CLK0 CLK_SEL 8 10 CLK1 CLK1 ...
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Divide-by-1/Divide-by-2 Clock Driver PIN NAME TQFP QFN QD3 QD3 QD2 QD2 QD1 QD1 QD0 QD0 1, 17, 18, 34, 28, 29 35, 38, 39, ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver MR, FSEL_, CLK_SEL CLK_ CLK_ (CLK_ IS CONNECTED Figure 1. Timing Diagram for Single-Ended Inputs CLK_ CLK_ Figure 2. Timing Diagram for Differential Inputs 8 ...
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Divide-by-1/Divide-by-2 Clock Driver Figure 3. Timing Diagram for MR Detailed Description The MAX9322 low-skew 1:15 differential clock driver reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver Single-Ended Inputs and V The differential clock input can be configured to accept a single-ended input when operating at V 3.0V to 3.8V. Connect V to the inverting or noninvert- BB ing input of ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver FSELA 75kΩ CLK0 V CC 75kΩ 75kΩ CLK0 75kΩ CLK1 V CC 75kΩ 75kΩ CLK1 75kΩ CLK_SEL 75kΩ 75kΩ ...
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LVECL/LVPECL 1:15 Differential Divide-by-1/Divide-by-2 Clock Driver TOP VIEW N. FSELA 5 FSELB 6 CLK0 7 CLK0 8 CLK_SEL 9 CLK1 10 CLK1 FSELC 13 FSELD 14 V ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2007 Maxim Integrated Products ...