ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 62

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Timer/Counter Interrupt Flag
Register – TIFR
62
ATtiny26(L)
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match A, interrupt is enabled. The corresponding interrupt at
vector $003 is executed if a compare match A occurs. The Compare Flag in
Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 compare match B, interrupt is enabled. The corresponding interrupt at
vector $004 is executed if a compare match B occurs. The Compare Flag in
Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 4..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1)
is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$006) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0)
is set (one) in the Timer/Counter Interrupt Flag Register – TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and
the data value in OCR1A – Output Compare Register 1A. OCF1A is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A
is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the
I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A Compare
Match interrupt is executed.
• Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and
the data value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hard-
Read/Write
Initial Value
Bit
$38 ($58)
Read/Write
Initial Value
R
R
7
–
0
0
OCF1A
R/W
R/W
0
6
0
OCF1B
R/W
R/W
0
5
0
R
0
R
4
–
0
R
0
R
3
–
0
TOV1
R/W
R/W
2
0
0
TOV0
R/W
R/W
1
0
0
1477J–AVR–06/07
R
0
–
0
R
0
TIFR