ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet
ATTINY26L8SU SL383
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ATTINY26L8SU SL383 Summary of contents
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Features • High-performance, Low-power AVR • RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – MIPS Throughput at 16 MHz • ...
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Pin Configuration ATtiny26(L) 2 (MOSI/DI/SDA/OC1A) PB0 (MISO/DO/OC1A) PB1 (SCK/SCL/OC1B) PB2 (OC1B) PB3 VCC GND (ADC7/XTAL1) PB4 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 (ADC10/RESET) PB7 NC 1 (OC1B) PB3 VCC 4 GND (ADC7/XTAL1) PB4 7 (ADC8/XTAL2) PB5 ...
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... ATtiny26( highly responsive to external events, still featuring the lowest power consumption while in the Power-down mode. The device is manufactured using Atmel’s high density non-volatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny26( powerful microcontroller that provides a highly flexible and cost effec- tive solution to many embedded control applications ...
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Block Diagram ATtiny26(L) 4 Figure 1. The ATtiny26(L) Block Diagram VCC GND PROGRAM STACK COUNTER POINTER PROGRAM SRAM FLASH AVCC INSTRUCTION GENERAL REGISTER PURPOSE REGISTERS X INSTRUCTION Y DECODER CONTROL ALU LINES STATUS REGISTER PROGRAMMING ISP INTERFACE LOGIC DATA REGISTER ...
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Pin Descriptions VCC GND AVCC Port A (PA7..PA0) Port B (PB7..PB0) XTAL1 XTAL2 1477J–AVR–06/07 Digital supply voltage pin. Digital ground pin. AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally connected ...
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... Resources ATtiny26( comprehensive set of development tools, application notes and datasheets are avail- able for download on http://www.atmel.com/avr. 1477J–AVR–06/07 ...
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About Code Examples 1477J–AVR–06/07 This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all ...
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AVR CPU Core Architectural Overview ATtiny26(L) 8 The fast-access Register File concept contains 32 x 8-bit general purpose working reg- isters with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic ...
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General Purpose Register File 1477J–AVR–06/07 The AVR uses a Harvard architecture concept with separate memories and buses for program and data memories. The program memory is accessed with a two stage pipelining. While one instruction is being executed, the next ...
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X-register, Y-register, and Z- register ALU – Arithmetic Logic Unit ATtiny26(L) 10 All of the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exceptions are the five constant arithmetic and ...
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Status Register – SREG 1477J–AVR–06/07 The AVR Status Register – SREG – at I/O space location $3F is defined as: Bit $3F ($5F Read/Write R/W R/W R/W Initial Value • Bit ...
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Stack Pointer – SP Program and Data Addressing Modes Register Direct, Single Register Rd ATtiny26(L) 12 The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space loca- tion $3D ($5D). As the ATtiny26(L) data memory has ...
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Register Direct, Two Registers Rd and Rr I/O Direct Data Direct 1477J–AVR–06/07 Figure 6. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 7. I/O ...
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Data Indirect with Displacement Data Indirect Data Indirect with Pre- decrement ATtiny26( 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. Figure 9. Data Indirect with Displacement ...
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Data Indirect with Post- increment Constant Addressing Using the LPM Instruction 1477J–AVR–06/07 The X-, Y-, or Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or Z-register. Figure 12. Data Indirect Addressing with ...
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Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL ATtiny26(L) 16 Figure 14. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). ...
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Memories 1477J–AVR–06/07 The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 16 shows the parallel instruction fetches and instruction executions enabled by ...
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In-System Programmable Flash Program Memory SRAM Data Memory ATtiny26(L) 18 Figure 18. On-chip Data SRAM Access Cycles T1 System Clock Ø Address Prev. Address Data WR Data RD The ATtiny26(L) contains 2K bytes On-chip In-System Programmable Flash memory for program ...
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EEPROM Data Memory EEPROM Read/Write Access EEPROM Address Register – EEAR 1477J–AVR–06/07 The five different addressing modes for the data memory cover: Direct, Indirect with Dis- placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers ...
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EEPROM Data Register – EEDR EEPROM Control Register – EECR ATtiny26(L) 20 Bit $1D ($3D) MSB Read/Write R/W R/W R/W Initial Value • Bit 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation, ...
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EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption 1477J–AVR–06/07 • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set ...
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I/O Memory ATtiny26(L) 22 The I/O space definition of the ATtiny26(L) is shown in Table 2 (1) Table 2. ATtiny26(L) I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3D ($5D) SP Stack Pointer $3B ($5B) GIMSK General ...
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Table 2. ATtiny26(L) I/O Space Address Hex Name Function $06($26) ADCSR ADC Control and Status Register $05($25) ADCH ADC Data Register High $04($24) ADCL ADC Data Register Low Note: 1. Reserved and unused locations are not shown in ...
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System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O Flash Clock – clk FLASH ADC Clock – clk ADC ATtiny26(L) 24 Figure 20 presents the principal clock systems in ...
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Internal PLL for Fast Peripheral Clock Generation – clk PCK 1477J–AVR–06/07 The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the ...
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Clock Sources ATtiny26(L) 26 The device has the following clock source options, selectable by Flash Fuse bits as shown below on Table 3. The clock from the selected source is input to the AVR clock generator, and routed to the ...
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Default Clock Source Crystal Oscillator 1477J–AVR–06/07 each time-out is shown in Table 5. The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics section. Table 5. Number of Watchdog Oscillator Cycles Typ Time-out (V = ...
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Low-frequency Crystal Oscillator ATtiny26(L) 28 The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 7. Table 7. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time CKSEL0 SUT1..0 from Power-down (1) 0 ...
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External RC Oscillator 1477J–AVR–06/07 For timing insensitive applications, the external RC configuration shown in Figure 23 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the ...
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... At 5V, 25°C and 1.0 MHz Oscillator frequency selected, this calibration gives a fre- quency within ± the nominal frequency. Using run-time calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V and Temperature. When this oscillator is used as the chip ...
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External Clock 1477J–AVR–06/07 will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not ...
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High Frequency PLL Clock – PLL CLK ATtiny26(L) 32 There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator for the use of the Peripheral Timer/Counter1 and for the system clock source. When ...
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System Control and Reset 1477J–AVR–06/07 The ATtiny26(L) provides four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. To use the PB7/RESET pin ...
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Power-on Reset ATtiny26(L) 34 Table 16. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold (1) Voltage (falling) V RESET Pin Threshold Voltage RST Minimum pulse width on t RST RESET Pin Brown-out Reset Threshold ...
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External Reset 1477J–AVR–06/07 Figure 26. MCU Start-up, RESET Tied to VCC V POT VCC V RST RESET t TOUT TIME-OUT INTERNAL RESET Figure 27. MCU Start-up, RESET Controlled Externally V POT VCC RESET TIME-OUT INTERNAL RESET An External Reset is ...
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Brown-out Detection Watchdog Reset ATtiny26(L) 36 ATtiny26(L) has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is enabled (BODEN programmed), and ...
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MCU Status Register – MCUSR 1477J–AVR–06/07 Bit $34 ($54) – – – Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny26(L) and ...
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Power Management and Sleep Modes MCU Control Register – MCUCR ATtiny26(L) 38 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the ...
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Idle Mode ADC Noise Reduction Mode Power-down Mode 1477J–AVR–06/07 • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag ...
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Standby Mode Table 19. Active Clock Domains and Wake-up Sources in the different Sleep Modes. Active Clock domains clk clk clk Sleep Mode CPU FLASH Idle X ADC Noise Reduction Power-down (1) Standby Notes: 1. Only recommended with external crystal ...
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Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins 1477J–AVR–06/07 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep ...
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ATtiny26(L) 42 and the input signal is left floating or have an analog signal level close to V input buffer will use excessive power. /2, the CC 1477J–AVR–06/07 ...
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I/O Ports Introduction 1477J–AVR–06/07 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin ...
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Ports as General Digital I/O Configuring the Pin ATtiny26(L) 44 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 32 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 32. General Digital I/O ...
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Reading the Pin Value 1477J–AVR–06/07 difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input ...
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ATtiny26(L) 46 signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in ...
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Digital Input Enable and Sleep Modes 1477J–AVR–06/07 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...
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Unconnected Pins Alternate Port Functions ATtiny26( some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described ...
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Table 22 summarizes the function of the overriding signals. The pin and port indexes from Figure 35 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table ...
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MCU Control Register – MCUCR Alternate Functions of Port A ATtiny26(L) 50 The MCU Control Register contains control bits for general MCU functions. Bit $35 ($55) – PUD SE Read/Write R R/W R/W Initial Value 0 0 ...
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AIN0: Analog Comparator Positive input and ADC5: ADC input channel 5 port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator or analog to ...
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ATtiny26(L) 52 Table 25. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AREF/PCINT1 PUOE ADMUX[REFS0] PUOV 0 DDOE ADMUX[REFS0] DDOV 0 PVOE 0 PVOV 0 (1) DIEOE PCINT1_ENABLE • (2) ~ ADMUX[REFS0] DIEOV 1 DI PCINT1 AIO ANALOG REFERENCE ...
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Alternate Functions Of Port B 1477J–AVR–06/07 Port B has an alternate functions for the ADC, Clocking, Timer/Counters, USI, SPI pro- gramming and pin change interrupt. The ADC is described in “Analog to Digital Converter” on page 96, Clocking in “AVR ...
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ATtiny26(L) 54 PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the ...
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OC1B: Output Compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin ...
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Table 27. Overriding Signals for Alternate Functions in PB7..PB4 Signal PB7/ADC10/RESET/ Name PCINT1 (1) PUOE RSTDSBL PUOV 1 (1) DDOE RSTDSBL DDOV 0 PVOE 0 PVOV 0 (2) DIEOE PCINT1_ENABLE | RSTDSBL (2) DIEOV PCINT1_ENABLE • (5) (1) ~ RSTDSBL ...
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Table 28. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/OC1B/PCINT0 PUOE 0 PUOV 0 DDOE 0 DDOV 0 (1) PVOE OC1B_ENABLE PVOV OC1B DIEOE PCINT0_ENABLE ~OC1B_ENABLE DIEOV 1 DI PCINT0 AIO – Notes: 1. Enabling of the Timer/Counter1 ...
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Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B ...
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Interrupts Interrupt Vectors 1477J–AVR–06/07 The ATtiny26(L) provides eleven interrupt sources. These interrupts and the separate Reset Vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set ...
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Interrupt Handling Interrupt Response Time General Interrupt Mask Register – GIMSK ATtiny26(L) 60 $00B sei … … … The ATtiny26(L) has two 8-bit Interrupt Mask Control Registers; GIMSK – General Inter- rupt Mask Register and TIMSK – Timer/Counter Interrupt Mask ...
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General Interrupt Flag Register – GIFR Timer/Counter Interrupt Mask Register – TIMSK 1477J–AVR–06/07 interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin. Activity on the pin will cause an interrupt request ...
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Timer/Counter Interrupt Flag Register – TIFR ATtiny26(L) 62 Read/Write R R/W R/W Initial Value • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny26(L) and always reads as zero. • Bit ...
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Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B Compare ...
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External Interrupt Pin Change Interrupt ATtiny26(L) 64 The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is configured as an output. This feature provides a way of ...
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Table 30. Alternative Functions Control Register[Bit Name] which Pin Alternate Function set the Alternate Function PA3 AREF ADMUX[REFS0] PA6 Analog Comparator ACSR[ACD] PA7 Analog Comparator ACSR[ACD] PB0 USI Two-wire mode USICR[USIWM1] USI Three-wire mode USICR[USIWM1,USIWM0] TC1 compare/PWM TCCR1A[COM1A1,COM1A0,PWM1A] PB1 ...
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Timer/Counters Timer/Counter0 Prescaler ATtiny26(L) 66 The ATtiny26(L) provides two general purpose 8-bit Timer/Counters. The Timer/Counters have separate prescaling selection from the separate prescaler. The Timer/Counter0 clock (CK) as the clock timebase. The Timer/Counter1 has two clocking modes, a synchronous mode ...
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Timer/Counter1 Prescaler 8-bit Timer/Counter0 1477J–AVR–06/07 Figure 37 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384 and stop in synchronous. The clock options are described in ...
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Timer/Counter0 Control Register – TCCR0 ATtiny26(L) 68 Figure 38. Timer/Counter0 Block Diagram Bit $33 ($53) – – – Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are ...
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Timer/Counter0 – TCNT0 8-bit Timer/Counter1 1477J–AVR–06/07 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed ...
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ATtiny26(L) 70 Figure 39. Timer/Counter1 Synchronization Register Block Diagram Input syncronization IO-registers registers OCR1A OCR1A_SI OCR1B OCR1B_SI OCR1C OCR1C_SI TCCR1A TCCR1A_SI TCCR1B TCCR1B_SI TCNT1 TCNT1_SI OCF1A OCF1A_SI OCF1B OCF1B_SI TOV1 TOV1_SI PCKE PCK SYNC 1CK delay MODE ...
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Figure 40. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ TIMER INT. MASK TIMER INT. FLAG REGISTER (TIMSK) REGISTER (TIFR) TIMER/COUNTER1 TIMER/COUNTER1 T/C CLEAR (TCNT1) 8-BIT COMPARATOR 8-BIT COMPARATOR T/C1 ...
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Timer/Counter1 Control Register A – TCCR1A ATtiny26(L) 72 Bit $30 ($50) COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value • Bits 7, 6 – COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and ...
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Timer/Counter1 Control Register B – TCCR1B 1477J–AVR–06/07 Writing a logical one to this bit forces a change in the Compare Match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written ...
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Timer/Counter1 – TCNT1 Timer/Counter1 Output Compare RegisterA – OCR1A ATtiny26(L) 74 • Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits and 0 The Clock Select bits and 0 define the prescaling source ...
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Timer/Counter1 Output Compare RegisterB – OCR1B Timer/Counter1 Output Compare RegisterC – OCR1C PLL Control and Status Register – PLLCSR 1477J–AVR–06/07 ware write that sets TCNT1 and OCR1A to the same value does not generate a compare match. A compare match ...
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Timer/Counter1 Initialization for Asynchronous Mode Timer/Counter1 in PWM Mode ATtiny26(L) 76 When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL reference clock. If PLL is selected as a system ...
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Table 35. Compare Mode Select in PWM Mode COM1x1 COM1x0 Effect on Output Compare Pins OC1x not connected OC1x not connected. OC1x cleared on compare match. Set when TCNT1 = $01 OC1x set one prescaled ...
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ATtiny26(L) 78 Table 36. PWM Outputs OCR1x = $00 or OCR1C COM1x1 COM1x0 OCR1x OCR1C OCR1C OCR1C In PWM mode, the Timer Overflow ...
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Table 37. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency (kHz) Clock Selection 20 PCK/16 30 PCK/16 40 PCK/8 50 PCK/8 60 PCK/8 70 PCK/4 80 PCK/4 90 PCK/4 100 PCK/4 110 PCK/4 120 PCK/4 130 PCK/2 ...
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Watchdog Timer Watchdog Timer Control Register – WDTCR ATtiny26(L) 80 The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value other V levels. By controlling the Watchdog ...
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In the same operation, write a logical one to WDCE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock ...
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Universal Serial Interface – USI Overview ATtiny26(L) 82 The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less ...
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Register Descriptions USI Data Register – USIDR USI Status Register – USISR 1477J–AVR–06/07 Bit $0F ($2F) MSB Read/Write R/W R/W R/W Initial Value The USI uses no buffering of the serial register, i.e., when ...
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USI Control Register – USICR ATtiny26( the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in Two- wire mode. A counter overflow interrupt will wakeup the processor from Idle sleep mode. • Bit ...
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Bit 5..4 – USIWM1..0: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the ...
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ATtiny26(L) 86 • Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of ...
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Functional Descriptions Three-wire Mode 1477J–AVR–06/07 The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if ...
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SPI Master Operation Example ATtiny26(L) 88 shifted by one) at negative edges. External clock mode 1 (USICS0 = 1) uses the oppo- site edges versus mode 0, i.e., samples data at negative and changes the output at positive edges. The ...
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SPI Slave Operation Example 1477J–AVR–06/07 The following code demonstrates how to use the USI module as a SPI Master with max- imum speed (fsck = fck/2): SPITransfer_Fast: out USIDR,r16 ldi r16,(1<<USIWM0)+(0<<USICS0)+(1<<USITC) ldi r17,(1<<USIWM0)+(0<<USICS0)+(1<<USITC)+(1<<USICLK) out USICR,r16 ; MSB out USICR,r17 out ...
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Two-wire Mode ATtiny26(L) 90 the master device, and when the transfer is completed the data received from the mas- ter is stored back into the r16 register. Note that the first two instructions is for initialization only and needs only ...
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Figure 48. Two-wire Mode, Typical Timing Diagram SDA SCL ADDRESS R Referring to the timing diagram (Figure 48.), a bus transfer involves the following steps: 1. The a start condition ...
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Start Condition Detector Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt ATtiny26(L) 92 The start condition detector is shown in Figure 49. The SDA line is delayed (in the range of ...
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Analog Comparator Analog Comparator Control and Status Register – ACSR 1477J–AVR–06/07 The Analog Comparator compares the input values on the positive pin PA6 (AIN0) and negative pin PA7 (AIN1). When the voltage on the positive pin PA6 (AIN0) is higher ...
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ATtiny26(L) 94 • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE ...
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Table 42. Analog Comparator Input Selection ACME ADEN MUX3... XXXX 1 1 XXXX 1 0 0000 1 0 0001 1 0 0010 1 0 0011 1 0 0100 1 0 0101 1 0 0110 1 0 0111 ...
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Analog to Digital Converter Features ATtiny26(L) 96 • 10-bit Resolution • ±2 LSB Absolute Accuracy • 0.5 LSB Integral Non-linearity • Optional Offset Cancellation • 260 µs Conversion Time • 11 Multiplexed Single Ended Input Channels • 8 ...
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Operation 1477J–AVR–06/07 Figure 51. Analog to Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER VCC AREF INTERNAL 2.56 V REFERENCE GND INTERNAL 1.18 V REFERENCE ADC10 ADC9 ADC8 ADC7 ADC6 POS. ADC5 INPUT MUX ADC4 ...
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Prescaling and Conversion Timing ATtiny26(L) 98 minal, otherwise the gain stage will saturate at 0V (GND). This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ...
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The successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz lower resolution than 10 bits is needed, the input clock fre- quency to the ADC can be as high as 1000 kHz ...
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Changing Channel or Reference Selection ATtiny26(L) 100 Figure 54. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Sample & Hold MUX and REFS Update Figure 55. ADC Timing Diagram, Free ...
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ADC Noise Canceler Function ADC Conversion Result 1477J–AVR–06/07 Special care should be taken when changing differential channels. Once a differential channel has been selected, the gain stage may take as much as 125 µs to stabilize to the new value. ...
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ATtiny26(L) 102 Figure 56. Differential Measurement Range Output Code 0x3FF 0x000 0 Table 44. Correlation Between Input Voltage and Output Codes V ADCn /GAIN ADCm REF V + (1023/1024) V /GAIN ADCm REF V + (1022/1024) V ...
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ADC Multiplexer Selection Register – ADMUX 1477J–AVR–06/07 Bit $07 ($27) REFS1 REFS0 ADLAR Read/Write R/W R/W R/W Initial Value • Bit 7, 6 – REFS1, REFS0: Reference Selection Bits These bits select the voltage ...
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ATtiny26(L) 104 Table 46. Input Channel and Gain Selections Single Ended Positive Differential MUX4..0 Input 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 01000 ADC8 01001 ADC9 01010 ADC10 01011 01100 (1) ...
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ADC Control and Status Register – ADCSR 1477J–AVR–06/07 Bit $06 ($26) ADEN ADSC ADFR Read/Write R/W R/W R/W Initial Value • Bit 7 – ADEN: ADC Enable Writing a logical “1” to this bit ...
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ADC Data Register – ADCL and ADCH ADLAR = 0 ADLAR = 1 ATtiny26(L) 106 • Bits 2..0 – ADPS2..0: ADC Prescaler Select Bits These bits determine the division factor between the CK frequency and the input clock to the ...
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Scanning Multiple Channels ADC Noise Canceling Techniques Offset Compensation Schemes 1477J–AVR–06/07 Since change of analog channel always is delayed until a conversion is finished, the Free Running mode can be used to scan multiple channels without interrupting the con- verter. ...
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ATtiny26(L) 108 Figure 57. ADC Power Connections (MOSI/DI/SDA/OC1A) PB0 1 (MISO/DO/OC1A) PB1 2 (SCK/SCL/OC1B) PB2 3 (OC1B) PB3 4 VCC 5 GND 6 (ADC7/XTAL1) PB4 7 8 (ADC8/XTAL2) PB5 (ADC9/INT0/T0) PB6 9 10 (ADC10/RESET) PB7 PA0 (ADC0 ...
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Memory Programming Program and Data Memory Lock Bits 1477J–AVR–06/07 The ATtiny26 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 49. The Lock bits can only ...
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Fuse Bits ATtiny26(L) 110 The ATtiny26 has two Fuse bytes. Table 50 and Table 51 describe briefly the functional- ity of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as ...
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... EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in normal mode. All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. ...
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ATtiny26(L) 112 Figure 58. Parallel Programming WR XA0 XA1/BS2 PAGEL/BS1 OE RDY/BSY +12 V Table 54. Pin Name Mapping Signal Name in Programming Mode Pin Name WR PB0 XA0 PB1 (1) XA1/BS2 PB2 (1) PAGEL/BS1 PB3 OE PB5 RDY/BSY PB6 ...
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Table 56. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or low address byte determined BS1 Load Data (High or Low data byte for ...
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Parallel Programming Enter Programming Mode Considerations for Efficient Programming ATtiny26(L) 114 The following algorithm puts the device in parallel programming mode: Step 2-7 must be completed within 64ms. 1. Set Prog_enable pins listed in Table 55 on page 112, RESET ...
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Chip Erase Programming the Flash 1477J–AVR–06/07 The Chip Erase will erase the Flash and EEPROM bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before ...
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ATtiny26(L) 116 F. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte ($00 - $03). 4. Give XTAL1 a ...
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Programming the EEPROM 1477J–AVR–06/07 Figure 60. Programming the Flash Waveforms $10 ADDR. LOW DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH DATA XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE Note: 1. “XX” is ...
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Reading the Flash Reading the EEPROM Programming the Fuse Low Bits ATtiny26(L) 118 Figure 61. Programming the EEPROM Waveforms A B $11 ADDR. LOW DATA DATA XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE The algorithm for reading the ...
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Programming the Fuse High Bits Programming the Lock Bits Reading the Fuse and Lock Bits 1477J–AVR–06/07 The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 115 for details on Command and ...
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Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics ATtiny26(L) 120 Figure 63. Mapping Between BS1, BS2 and the Fuse- and Lock-bits During Read Fuse Low Byte Lock Bits Fuse High Byte BS2 The algorithm for reading the ...
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Figure 65. Parallel Programming Timing, Loading Sequence with Timing (1) Requirements LOAD ADDRESS (LOW BYTE) t XLXH XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) XA0 XA1/BS2 Note: 1. The timing requirements shown in Figure 64 (i.e loading operation. ...
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ATtiny26(L) 122 Table 58. Parallel Programming Characteristics, V Symbol Parameter V Programming Enable Voltage PP I Programming Enable Current PP t Data and Control Valid before XTAL1 High DVXH t XTAL1 Low to XTAL1 High XLXH t XTAL1 Pulse Width ...
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Serial Downloading Serial Programming Pin Mapping 1477J–AVR–06/07 Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). ...
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SPI Serial Programming Algorithm ATtiny26(L) 124 When writing serial data to the ATtiny26, data is clocked on the rising edge of SCK. When reading data from the ATtiny26, data is clocked on the falling edge of SCK. See Figure 68, ...
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Data Polling Flash Data Polling EEPROM 1477J–AVR–06/07 When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value $FF. At the time the device is ready for a new ...
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Table 61. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory Page 0100 H000 Write Program Memory Page 0100 1100 Read EEPROM Memory 1010 0000 Write ...
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Serial Programming Characteristics 1477J–AVR–06/07 Figure 69. Serial Programming Timing MOSI t OVSH SCK MISO Table 62. Serial Programming Characteristics, T (1) (Unless Otherwise Noted) Symbol Parameter 1/t Oscillator Frequency (V CLCL t Oscillator Period (V = 2.7 - 5.5 V) ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-0. Voltage on RESET with Respect to Ground ....-0.5V to +13.0V Maximum ...
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T = -40°C to 85° 2.7V to 5.5V (unless otherwise noted) (Continued Symbol Parameter Power Supply Current I CC (6) Power-down mode Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input Leakage Current ...
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External Clock Drive Waveforms External Clock Drive ATtiny26(L) 130 Figure 70. External Clock Drive Waveforms V IH1 V IL1 Table 63. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low ...
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ADC Characteristics Table 65. ADC Characteristics, Single Ended Channels, T Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL, Quantization Error, Gain and Offset Error) Integral Non-Linearity (INL) Differential Non-Linearity (DNL) Gain Error Offset error Clock Frequency Conversion Time AVCC Analog ...
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Table 66. ADC Characteristics, Differential Channels, T Symbol Parameter Resolution Absolute Accuracy Integral Non-Linearity (INL) (Accuracy after Calibration for Offset and Gain Error) Gain Error Offset Error Clock Frequency Conversion Time AVCC Analog Supply Voltage V Reference Voltage REF V ...
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ATtiny26 Typical Characteristics Active Supply Current 1477J–AVR–06/07 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A ...
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ATtiny26(L) 134 Figure 72. Active Supply Current vs. Frequency ( MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY Figure 73. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V ...
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Figure 74. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 2.5 3 Figure 75. Active Supply Current vs. V ACTIVE SUPPLY CURRENT ...
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ATtiny26(L) 136 Figure 76. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 2.5 3 Figure 77. Active Supply Current vs. V ACTIVE ...
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Idle Supply Current 1477J–AVR–06/07 Figure 78. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 1.5 2 2.5 Figure 79. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY ...
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ATtiny26(L) 138 Figure 80. Idle Supply Current vs. Frequency ( MHz) IDLE SUPPLY CURRENT vs. FREQUENCY Figure 81. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. ...
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Figure 82. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 4 MHz 3.5 3 2.5 2 1 2.5 3 Figure 83. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. ...
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ATtiny26(L) 140 Figure 84. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V INTERNAL RC OSCILLATOR, 1 MHz 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 Figure 85. Idle Supply Current vs. V IDLE SUPPLY ...
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Power-down Supply Current 1477J–AVR–06/07 Figure 86. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 2.5 3 Figure 87. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs. V 1.8 1.6 ...
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Standby Supply Current ATtiny26(L) 142 Figure 88. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs 2.5 3 Figure 89. Standby Supply Current vs. V Disabled) STANDBY ...
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Figure 90. Standby Supply Current vs. V Disabled) STANDBY SUPPLY CURRENT vs MHz RESONATOR, WATCHDOG TIMER DISABLED 2.5 3 Figure 91. Standby Supply Current vs. V Disabled) STANDBY SUPPLY ...
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ATtiny26(L) 144 Figure 92. Standby Supply Current vs. V STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 2.5 3 Figure 93. Standby Supply Current vs. V ...
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Figure 94. Standby Supply Current vs. V STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 120 100 2.5 3 Figure 95. Standby Supply Current vs. V Disabled) STANDBY SUPPLY CURRENT ...
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Pin Pull-up ATtiny26(L) 146 Figure 96. Standby Supply Current vs. V STANDBY SUPPLY CURRENT vs MHz XTAL, WATCHDOG TIMER DISABLED 180 160 140 120 100 2.5 3 Figure 97. I/O Pin Pull-up ...
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Figure 98. I/O Pin Pull-up Resistor Current vs. Input Voltage (V I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 80 85 °C 25 °C 70 -40 ° 0.5 1 Figure 99. ...
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Pin Driver Strength ATtiny26(L) 148 Figure 100. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 -40 °C 25 ° ° 0.5 1 ...
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Figure 102. I/O Pin Source Current vs. Output Voltage (V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE 30 -40 ° °C 85 ° 0.5 1 Figure 103. I/O Pin Sink Current ...
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ATtiny26(L) 150 Figure 104. I/O Pin Sink Current vs. Output Voltage (V I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 Figure 105. Reset Pin as I/O – Source Current vs. Output ...
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Figure 106. Reset Pin as I/O – Source Current vs. Output Voltage (V RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE 2.5 -40 ° °C 1.5 85 ° 0.5 1 Figure ...
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Pin Thresholds and Hysteresis ATtiny26(L) 152 Figure 108. Reset Pin as I/O – Sink Current vs. Output Voltage (V RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE 4.5 4 3.5 3 2.5 2 1 ...
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Figure 110. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs 1 2.5 3 Figure 111. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.7 ...
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ATtiny26(L) 154 Figure 112. Reset Pin as I/O – Input Threshold Voltage vs Reset Pin Read as “1”) IH RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1 2.5 ...
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Figure 114. Reset Pin as I/O – Pin Hysteresis vs. V RESET PIN AS I/O - PIN HYSTERESIS vs. V 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 Figure 115. Reset Input Threshold Voltage vs. V ...
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ATtiny26(L) 156 Figure 116. Reset Input Threshold Voltage vs. V RESET INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 85 °C 25 °C 1 -40 °C 0 2.5 3 Figure 117. Reset Input Pin Hysteresis vs. V RESET ...
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BOD Thresholds and Analog Comparator Offset 1477J–AVR–06/07 Figure 118. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRESHOLDS vs. TEMPERATURE 4.3 4.2 4.1 4 3.9 3.8 -50 -40 -30 -20 -10 0 Figure 119. BOD Thresholds vs. Temperature (BOD ...
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ATtiny26(L) 158 Figure 120. Bandgap Voltage vs. V 1.236 1.234 1.232 1.23 1.228 1.226 1.224 1.222 1.22 1.218 1.216 2.5 3 3.5 Figure 121. Analog Comparator Offset Voltage vs. Common Mode Voltage (V ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE ...
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Internal Oscillator Speed 1477J–AVR–06/07 Figure 122. Analog Comparator Offset Voltage vs. Common Mode Voltage (V ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 Figure 123. Watchdog Oscillator ...
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ATtiny26(L) 160 Figure 124. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.9 8.4 7.9 7.4 6.9 6.4 -60 -40 -20 Figure 125. Calibrated 8 MHz RC Oscillator Frequency vs. V CALIBRATED 8MHz ...
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Figure 126. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 17.5 15.5 13.5 11.5 9.5 7.5 5.5 3 Figure 127. Calibrated 4 MHz RC ...
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ATtiny26(L) 162 Figure 128. Calibrated 4 MHz RC Oscillator Frequency vs. V CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. V 4.4 4.3 4.2 4.1 4 3.9 3.8 3.7 3.6 3.5 3.4 2 2.5 3 Figure 129. Calibrated 4 MHz RC Oscillator ...
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Figure 130. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.15 2.1 2.05 2 1.95 1.9 1.85 1.8 1.75 -60 -40 -20 Figure 131. Calibrated 2 MHz RC Oscillator Frequency vs. V ...
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ATtiny26(L) 164 Figure 132. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 4.3 3.8 3.3 2.8 2.3 1.8 1.3 0 Figure 133. Calibrated 1 MHz ...
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Figure 134. Calibrated 1 MHz RC Oscillator Frequency vs. V CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. V 1.1 1.05 1 0.95 0.9 0.85 2 2.5 3 Figure 135. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1MHz ...
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Current Consumption of Peripheral Units ATtiny26(L) 166 Figure 136. Brown-out Detector Current vs. V BROWNOUT DETECTOR CURRENT vs. V 0.035 0.03 0.025 -40 °C 0.02 25 °C 85 °C 0.015 0.01 0.005 0 2 2.5 3 Figure 137. ADC Current ...
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Figure 138. AREF External Reference Current vs. V AREF EXTERNAL REFERENCE CURRENT vs. VCC 250 200 150 100 2.5 3 Figure 139. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 120 100 80 60 ...
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Current Consumption in Reset and Reset Pulsewidth ATtiny26(L) 168 Figure 140. Programming Current vs. V PROGRAMMING CURRENT vs. VCC 2.5 3 Figure 141. Reset Supply Current vs. V (0.1 - 1.0 MHz, Excluding ...
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Figure 142. Reset Supply Current vs MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP ...
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Register Summary Address Name Bit 7 $3F ($5F) SREG I $3E ($5E) Reserved $3D ($5D) SP SP7 $3C ($5C) Reserved $3B ($5B) GIMSK - $3A ($5A) GIFR - $39 ($59) TIMSK - $38 ($58) TIFR - $37 ($57) Reserved $36 ...
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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl, K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...
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Instruction Set Summary (Continued) Mnemonic Operands Description LD Rd, Y Load Indirect LD Rd, Y+ Load Indirect and Post-inc. LD Rd, -Y Load Indirect and Pre-dec. LDD Rd,Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ ...
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... Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc- tive). Also Halide free and fully Green. ...
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Packaging Information 20P3 A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 ...
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ATtiny26(L) 175 ...
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Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ...
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Errata ATtiny26 Rev. B/C/D 1477J–AVR–06/07 The revision letter refers to the revision of the device. • First Analog Comparator conversion may be delayed 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising ...
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Datasheet Revision History Rev. 1477I-06/07 Rev. 1477I-05/06 Rev. 1477H-04/06 Rev. 1477G-03/05 Rev. 1477F-12/04 Rev. 1477E-10/03 ATtiny26(L) 178 Please note that the referring page numbers in this section are referred to this docu- ment. The referring revision in this section are ...
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Rev. 1477D-05/03 Rev. 1477C-09/02 Rev. 1477B-04/02 1477J–AVR–06/07 7. Updated V , INL and Gain Error in “ADC Characteristics” on page 131 and INT page 132. Fixed typo in “Absolute Accuracy” on page 132. 8. Added Figure 106 in “Pin Driver ...
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Rev. 1477A-03/02 ATtiny26(L) 180 1. Initial version. 1477J–AVR–06/07 ...
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Table of Contents 1477J–AVR–06/07 Features................................................................................................ 1 Pin Configuration................................................................................. 2 Description ........................................................................................... 3 Block Diagram ...................................................................................................... 4 Pin Descriptions.................................................................................................... 5 Resources ............................................................................................ 6 About Code Examples......................................................................... 7 AVR CPU Core ..................................................................................... 8 Architectural Overview.......................................................................................... 8 General Purpose Register File ............................................................................. 9 ...
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I/O Ports.............................................................................................. 43 Interrupts ............................................................................................ 59 External Interrupt............................................................................... 64 Timer/Counters .................................................................................. 66 Watchdog Timer................................................................................. 80 Universal Serial Interface – USI........................................................ 82 Analog Comparator ........................................................................... 93 Analog to Digital Converter .............................................................. 96 ATtiny26(L) ii Idle Mode ............................................................................................................ 39 ADC Noise Reduction ...
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Memory Programming..................................................................... 109 Program and Data Memory Lock Bits............................................................... 109 Fuse Bits........................................................................................................... 110 Signature Bytes ................................................................................................ 111 Calibration Byte ................................................................................................ 111 Page Size ......................................................................................................... 111 Parallel Programming Parameters, Pin Mapping, and Commands .................. 111 Parallel Programming ....................................................................................... 114 Serial ...
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ATtiny26(L) iv 1477J–AVR–06/07 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...