MACH111-10JC LATTICE [Lattice Semiconductor], MACH111-10JC Datasheet - Page 4

• Manufacturer Part Number: MACH111-10JC
• Description: High-Performance EE CMOS Programmable Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed fixed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
4
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
MACH111(SP)
MACH131(SP)
MACH211(SP)
MACH221(SP)
MACH231(SP)
I/O Pins
I/O Pins
Device
Figure 1. Overall Architecture of MACH 1 & 2 Devices
PAL Blocks
PAL Block
PAL Block
2
4
4
8
8
Macrocells per Block
MACH 1 & 2 Families
Dedicated Input
Clock/Input Pins
16
16
16
12
16
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
Array and
Allocator
I/Os per Block
®
blocks interconnected by a switch
16
16
8
6
8
Macrocells
Macrocells
PAL Block
Output
Buried
(note 1)
Product Terms per Block
I/O Cells
70
70
68
52
68
14051K-002
PAL Block
I/O Pins
I/O Pins