MACH111-10JC LATTICE [Lattice Semiconductor], MACH111-10JC Datasheet - Page 12

• Manufacturer Part Number: MACH111-10JC
• Description: High-Performance EE CMOS Programmable Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch
matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
12
(Common to bank of
Output Enable
Product Terms
• Patented Architecture
• Path Independent
• Logic/Routing Independent
• Guaranteed Fixed Timing
• Up to 16 Product Terms per Output
I/O Cells)
t PD (ns)
MACH 1 & 2 SpeedLocking
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
11
10
9
8
7
6
5
From Output
Macrocell
To Switch
Shared Expander Delay
5 ns
Matrix
8.8 ns
V
Parallel Expander Delay
5 PT
MACH 1 & 2 Families
CC
Figure 7. I/O Cell
5.8 ns
SpeedLocking
Product Terms
0 1
1 1
1 0
0 0
10 PT
6.6 ns
• Variable
• Path Dependent
• Logic/Routing Dependent Delays
• Unpredictable
• 4-5 Product Terms before Delays
15 PT
10.4 ns
Non-MACH
Non-MACH
7.4 ns
MACH 1 & 2
(MACH 2 only)
Macrocell
To Buried
14051K-007
14051K-001