MACH111-10JC LATTICE [Lattice Semiconductor], MACH111-10JC Datasheet - Page 11

• Manufacturer Part Number: MACH111-10JC
• Description: High-Performance EE CMOS Programmable Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
All flip-flops have asynchronous reset and preset. This is controlled by the common product terms
that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops
is illustrated in Table 11.
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
MACH111
MACH111SP
MACH131
MACH131SP
MACH211
Device
Register
Latch
Configuration
Number of Clocks Available
Table 11. Asynchronous Reset/Preset Operation
4
2
4
4
4
Table 10. Macrocell Clocks
AR
MACH 1 & 2 Families
0
0
1
1
0
0
0
1
1
1
1
AP
0
1
0
1
0
1
1
0
0
1
1
MACH211SP
MACH221
MACH221SP
MACH231
MACH231SP
CLK/LE
X
X
X
X
X
0
1
0
1
0
1
Device
See Table 9
See Table 9
Illegal
Illegal
Illegal
Q+
1
0
0
1
0
0
Number of Clocks Available
2
4
4
4
4
11