K4H280438F SAMSUNG [Samsung semiconductor], K4H280438F Datasheet - Page 15

• Manufacturer Part Number: K4H280438F
• Description: 128Mb F-die DDR SDRAM Specification
• Manufacturer: SAMSUNG [Samsung semiconductor]

AC Timming Parameters & Specifications
DDR SDRAM 128Mb F-die (x4, x8)
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
tWPRES
tDQSCK
Symbol
tDQSQ
tWPRE
tRPRE
tDQSS
tDQSH
tXSNR
tXSRD
tSLMR
tRPST
tDQSL
tDIPW
tPDEX
tWTR
tMRD
tREFI
tRFC
tRAS
tRCD
tRRD
tCCD
tDSS
tDSH
tDSC
tIPW
tWR
tCH
tDH
tRC
tRP
tCK
tAC
tHZ
tDS
tCL
tLZ
tIS
tIH
tIS
tIH
(DDR333@CL=2.5
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.45
0.45
1.75
0.67
-0.7
-0.7
-0.6
200
0.2
7.5
0.9
0.4
0.2
0.9
0.8
0.8
2.2
60
72
42
18
18
12
15
12
75
1
1
6
0
6
-
B3
Max
0.55
0.55
+0.6
+0.7
0.45
1.25
+0.7
+0.7
70K
1.1
0.6
1.1
7.8
1.5
12
12
(DDR266@CL=2.0
-0.75
-0.75
-0.75
1.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
200
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
2.2
7.5
65
75
45
20
20
15
15
15
75
1
1
0
-
A2
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
0.6
1.1
0.5
1.1
7.8
1.5
12
12
(DDR266@CL=2.5
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
1.75
0.67
200
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
0.5
0.5
2.2
7.5
65
75
45
20
20
15
15
10
15
75
1
1
0
-
B0
+0.75
+0.75
120K
Max
+0.75
+0.75
1.25
0.55
0.55
0.5
1.1
0.6
1.1
7.8
1.5
12
12
Rev. 1.1 May. 2004
(DDR200@CL=2.0
Min
0.45
0.45
0.75
0.25
0.35
0.35
15.6
0.67
-0.8
-0.8
-0.8
-0.8
200
0.9
0.4
0.2
0.2
0.9
1.1
1.1
1.1
1.1
0.6
0.6
2.5
80
70
80
48
20
20
15
15
10
16
10
1
1
0
2
-
DDR SDRAM
A0
120K
Max
0.55
0.55
+0.8
+0.8
1.25
+0.8
+0.8
0.6
1.1
0.6
1.1
1.5
12
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
Note
i,5.7
i,5.7
j, k
j, k
12
3
i,
i,
1
1
8
8
4