K4T56043QF-GCD5 SAMSUNG [Samsung semiconductor], K4T56043QF-GCD5 Datasheet - Page 21

• Manufacturer Part Number: K4T56043QF-GCD5
• Description: 256Mb F-die DDR2 SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

256Mb F-die DDR2 SDRAM
4. Differential data strobe
the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in sys-
tem design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is guaranteed by design and characterization. Note that
when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied
externally to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal refer-
ence/supply voltage levels, but the related specifications and device operation are guaranteed for the full volt-
age range specified.
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on
may be guaranteed by device design or tester correlation.
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
t
RPRE
DQS
DQS
WPRE
V
V
IH
IL
(ac)
(ac)
t
DMin
DS
t
t
CL
DQSQmax
D
<Data output (read) timing>
<Data input (write) timing>
t
DQSH
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V
V
IH
IL
(ac)
(ac)
DMin
t
t
QH
DS
D
Q
t
DQSL
DMin
Q
D
t
DH
V
V
IH
IL
(dc)
(dc)
t
DQSQmax
DMin
Q
D
t
DH
V
V
IH
IL
t
(dc)
WPST
(dc)
t
t
RPST
QH
Q
Rev. 1.5 Feb. 2005
DDR2 SDRAM