K4T56043QF-GCD5 SAMSUNG [Samsung semiconductor], K4T56043QF-GCD5 Datasheet

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... F-die DDR2 SDRAM 256Mb F-die DDR2 SDRAM Specification Version 1.5 February 2005 Page DDR2 SDRAM Rev. 1.5 Feb. 2005 ...

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... F-die DDR2 SDRAM Contents 0. Ordering Information 1. Key Feature 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pintout & Mechnical Dimension 2.2 Input/Output Function Description 2.3 Addressing 3. Absolute Maximum Rating 4. AC & DC Operating Conditions & Specifications Page DDR2 SDRAM Rev. 1.5 Feb. 2005 ...

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... All of Lead-free products are compliant for RoHS Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram” DDR2-533 4-4-4 K4T56043QF-GCD5 K4T56043QF-ZCD5 K4T56083QF-GCD5 K4T56083QF-ZCD5 ...

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... F-die DDR2 SDRAM 2. Package Pinout/Mechnical Dimension & Addressing 2.1 Package Pinout x4 package pinout (Top View) : 60ball FBGA Package 1 VDD NC VDDQ NC VDDL NC VSS VDD Notes: 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ground for the DLL. Ball Locations (x4) ...

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... F-die DDR2 SDRAM x8 package pinout (Top View) : 60ball FBGA Package 1 VDD DQ6 VDDQ DQ4 VDDL NC VSS VDD Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & ...

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... F-die DDR2 SDRAM FBGA Package Dimension(x4/x8 60- 0.45± ∅ 0.05 ∅0 #A1 11.00 ± 0.10 6.40 0.80 1. 3.20 (5.50) (0.90) (1.80) 11.00 ± 0.10 Page DDR2 SDRAM # A1 INDEX MARK 0.35± 0.05 MAX.1.20 Rev. 1.5 Feb. 2005 ...

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... Input Rank selection on systems with multiple Ranks considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM ODT Input signal for x4/x8 configurations. The ODT pin will be ignored if the Extended Mode Register Set(EMRS) is programmed to disable ODT ...

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... F-die DDR2 SDRAM 2.3 256Mb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 512Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 1Gb Configuration ...

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... Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1 ...

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... Parameter TOPER Operating Temperature 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. ...

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... F-die DDR2 SDRAM Differential input AC logic Level Symbol Parameter V (AC) AC differential input voltage ID V (AC) AC differential cross point voltage IX Notes (AC) specifies the input differential voltage |V ID LDQS or UDQS) and V is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V ...

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... DRAM uncertainty. Output slew rate load : Output (V OUT) 7. DRAM output slew rate specification applies to 400Mb/sec/pin, 533Mb/sec/pin and 667Mb/sec/pin speed bins. 8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and tQHS specification. Min Nom 12 ...

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... F-die DDR2 SDRAM IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Proposed Conditions IDD0 Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands ...

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... F-die DDR2 SDRAM Notes: 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combi- nations of EMRS bits 10 and 11 ...

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... IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 Normal IDD7 Symbol E6(DDR2-667@CL=5) D5(DDR2-533@CL=4) CC(DDR2-400@CL=3) IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 Normal IDD7 64Mx4(K4T56043QF) - D5(DDR2-533@CL=4) CC(DDR2-400@CL=3) - 100 - 110 - 160 - 150 - 165 - 5 - ...

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... F-die DDR2 SDRAM Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS Electrical Characteristics & AC Timing for DDR2-667/533/400 (0 ° ...

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... F-die DDR2 SDRAM Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Symbol Parameter DQ output access time tAC from CK/CK DQS output access tDQSCK time from CK/CK CK high-level width tCH CK low-level width tCL CK half period tHP Clock cycle time, CL=x ...

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... F-die DDR2 SDRAM Symbol Parameter Mode register set tMRD command cycle time Write postamble tWPST Write preamble tWPRE Address and control tIH(base) input hold time Address and control tIS(base) input setup time Read preamble tRPRE Read postamble tRPST Active to active ...

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... F-die DDR2 SDRAM Symbol Parameter Exit active power down tXARDS to read command (slow exit, lower power) CKE minimum pulse t CKE width (high and low pulse width) ODT turn-on delay t AOND ODT turn-on t AON ODT turn-on(Power- t AONPD Down mode) ODT turn-off delay ...

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... The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output tim- ing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal. 3. DDR2 SDRAM output slew rate test load Output slew rate is characterized under the test conditions as shown in the following figure. VDDQ ...

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... EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in sys- tem design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF ...

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... F-die DDR2 SDRAM Specific Notes for dedicated AC parameters 9. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing ...

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... F-die DDR2 SDRAM 18. tIS and tIH (input setup and hold) derating. 2.0 V/ns ∆tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 Com- 0.9 -11 mand/Ad- dress Slew 0.8 -25 rate 0.7 -43 (V/ns) 0.6 -67 0.5 -110 0.4 -175 0.3 -285 0.25 -350 0.2 -525 0.15 -800 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Com- mand/Ad- 0.8 -13 dress Slew ...

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... F-die DDR2 SDRAM For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the datasheet tIS(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS 19 ...

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... F-die DDR2 SDRAM culation is consistent. These notes are referenced in the “Timing parameters by speed grade” tables for DDR2-400/533/667 and DDR2-800. tHZ tRPST end point T2 T1 tHZ,tRPST end point 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input sig- ...

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... F-die DDR2 SDRAM 31. Input waveform timing is referenced from the input signal crossing at the V for a falling signal applied to the device under test. 32. Input waveform timing is referenced from the input signal crossing at the V for a falling signal applied to the device under test ...

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... F-die DDR2 SDRAM Revision History Version 1.0 (Jan. 2004) - Initial Release Version 1.1 (Jun. 2004) - Added Lead-Free part number in ordering information. - Changed IDD2P - Corrected Typo Version 1.2 (Aug. 2004) - Corrected the part number in ordering information. Version 1.3 (Jan. 2005) - Revised current test AC spec condition - Added derating table Version 1 ...