EM2420 ETC [List of Unclassifed Manufacturers], EM2420 Datasheet - Page 63

• Manufacturer Part Number: EM2420
• Description: 2.4 GHz IEEE 802.15.4 / ZigBee RF Transceiver
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Configuration Registers
The configuration of the EM2420 is done by
programming
registers. Complete descriptions of the
registers are given in the following tables.
After chip reset (from the RESETn pin or
programmable through the MAIN.RESETn
configuration bit), all the registers have
default values as shown in the tables.
Note that the MAIN register is only reset
by using the pin reset RESETn. When
writing to this register, all bits will get the
value written, not the default value. This
also means that the MAIN.RESETn bit
must be written both low and then high to
perform a chip reset through the serial
interface.
15
Registers, listed first in Table 11 below.
Accessing these registers will initiate the
change of an internal state or mode. There
are 33 normal 16-bits registers, also listed
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
Ember Part Number: 120-0049-000C
registers
Register
SNOP
SXOSCON
STXCAL
SRXON
STXON
STXONCCA
SRFOFF
SXOSCOFF
SFLUSHRX
SFLUSHTX
SACK
SACKPEND
SRXDEC
STXENC
the
are
16-bit
Strobe
Register type
S
S
S
S
S
S
S
S
S
S
S
S
S
S
configuration
Command
EM2420 Datasheet
Description
No Operation (has no other effect than reading out status-bits)
Turn on the crystal oscillator (set XOSC16M_PD = 0 and
BIAS_PD = 0)
Enable and calibrate frequency synthesizer for TX; go from RX /
TX to a wait state where only the synthesizer is running.
Enable RX
Enable TX after calibration (if not already performed)
Start TX in-line encryption if SPI_SEC_MODE ≠ 0
If CCA indicates a clear channel:
else do nothing
Disable RX/TX and frequency synthesizer
Turn off the crystal oscillator and RF
Flush the RX FIFO buffer and reset the demodulator. Always
read at least one byte from the RXFIFO before issuing the
SFLUSHRX command strobe
Flush the TX FIFO buffer
Send acknowledge frame, with pending field cleared.
Send acknowledge frame, with pending field set.
Start RXFIFO in-line decryption / authentication (as set by
SPI_SEC_MODE)
Start TXFIFO in-line encryption / authentication (as set by
SPI_SEC_MODE), without starting TX.
Enable calibration, then TX.
Start in-line encryption if SPI_SEC_MODE ≠ 0
in Table 11. Many of these registers are
for test purposes only, and need not be
accessed for normal operation of the
EM2420.
The FIFOs are accessed through two 8-bit
registers, TXFIFO and RXFIFO. The
TXFIFO register is write only. Data may
still be read out of the TXFIFO through
regular RAM access (see section RAM
access section on page 27), but data is
then not removed from the FIFO. Note that
the crystal oscillator must be active for all
FIFO and RAM access.
During the address transfer and while
writing to the TXFIFO, a status byte is
returned on the serial data output pin SO.
This status byte is described in Table 5 on
page 27.
All configuration and status registers are
described in the tables following Table 11.
EM2420
Page 63 of 89