EM2420 ETC [List of Unclassifed Manufacturers], EM2420 Datasheet - Page 30

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EM2420

Manufacturer Part Number
EM2420
Description
2.4 GHz IEEE 802.15.4 / ZigBee RF Transceiver
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet

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EM2420
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EMBER
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illustrated in Figure 10. The only exception
is that FIFO and RAM access must be
Figure 10. Multiple SPI Access Example
Microcontroller Interface and Pin Description
When used in a typical system, the EM2420
will interface to a microcontroller. This
microcontroller must be able to:
• Program the EM2420 into different
• Interface to the receive and transmit
• Interface to the CCA pin for clear
• Interface to the SFD pin for timing
Configuration interface
An
example is shown in Figure 11. The
microcontroller uses 4 I/O pins for the SPI
configuration interface (SI, SO, SCLK and
Ember Part Number: 120-0049-000C
modes, read and write buffered data,
and read back status information via
the
interface (SI, SO, SCLK and CSn).
FIFOs using the FIFO and FIFOP
status pins.
channel assessment.
information (particularly for beaconing
networks).
EM2420-to-microcontroller
4-wire
CSn
SO
SI
Command
SPI-bus
ADDR
Status
Strobe
ADDR
Status
configuration
Register
DATA
Read
interface
-
8MSB
EM2420 Datasheet
DATA
-
8LSB
ADDR
terminated by setting CSn high.
Status
CSn). SO should be connected to an input
at the microcontroller. SI, SCLK and CSn
must
Preferably the microcontroller should have
a hardware SPI interface.
The microcontroller pins connected to SI,
SO and SCLK can be shared with other
SPI-interface devices. SO is a high
impedance output as long as CSn is not
activated (active low). An internal pull-up
on the SO pin may be enabled in the
IOCFG0.SO_PULLUP configuration bit.
CSn should have an external pull-up
resistor or be set to a high level during
power down mode in order to prevent the
input from floating. SI and SCLK should be
set to a defined level to prevent the inputs
from floating.
TXFIFO
DATA
Status
be
ADDR
TXFIFO
Write
DATA
Status
microcontroller
ADDR+1
DATA
Status
EM2420
ADDR+2
Page 30 of 89
outputs.

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