PSD913F1-B-90JI ST Microelectronics, PSD913F1-B-90JI Datasheet - Page 17
PSD913F1-B-90JI
Manufacturer Part Number
PSD913F1-B-90JI
Description
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Manufacturer
ST Microelectronics
Datasheet
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Preliminary Information
Table 5.
PSD9XX
Pin
Descriptions
(cont.)
N/A = Not Applicable
**
*
numbers on other package types.
Table 6. I/O Port Latched Address Output Assignments*
Pin Name Pin*
The pin numbers in this table are for the PLCC package only. See the package information section for pin
PC7
PD0
PD1
PD2
V CC
GND
Refer to the I/O Port Section on how to enable the Latched Address Output function.
Microcontroller
8051XA (8-bit)
80C251 (page mode)
All other 8-bit
multiplexed
8-bit non-multiplexed
bus
1,16,26
(PLCC)
15, 38
11
10
9
8
Type
I/O
I/O
I/O
I/O
N/A
N/A
Address [3:0] Address [7:4]
N/A
Port A (3:0) Port A (7:4)
PC7 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. Input to the PLDs.
3. DBE — active-low Data Byte Enable input from 68HC912
This pin can be configured as a CMOS or Open Drain output.
PD0 pin of Port D. This port pin can be configured to have
the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
3. Input to the PLDs.
4. General Purpose PLD output.
PD1 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. Input to the PLDs.
3. General Purpose PLD output
4. CLKIN — clock input to the automatic power-down
PD2 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
2. Input to the PLDs.
3. General Purpose PLD output.
4. CSI — chip select input. When low, the MCU can access
Power pins
Ground pins
input port.
type MCUs.
port.
input port.
unit’s power-down counter, and the PLD AND array.
input port.
the PSD memory and I/O. When high, the PSD memory
blocks are disabled to conserve power.
Port A
Address [7:4]
N/A
N/A
Description
Address [11:8] N/A
Address [11:8] Address [15:12]
Address [3:0]
Address [3:0]
Port B (3:0)
Port B
Address [7:4]
Address [7:4]
Port B (7:4)
PSD9XX Family
13
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