HYS6472V4200GU Siemens, HYS6472V4200GU Datasheet - Page 13

• Manufacturer Part Number: HYS6472V4200GU
• Description: 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
• Manufacturer: Siemens

SPD-Table for PC66 modules:
Semiconductor Group
Byte#
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
0
1
2
3
4
5
6
7
8
9
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back ran-
dom column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
SDRAM Device Attributes :General
Minimum Clock Cycle Time at CAS Latency
= 2
Maximum data access time from Clock for
CL=2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time
Minimum Row Active to Row Active delay
tRRD
(for x16 SDRAM)
Description
13
Vcc tol +/- 10%
CS latency = 0
1, 2, 4, 8 & full
not supported
not supported
Self-Refresh,
non buffered/
t
CL = 2 & 3
SPD Entry
ccd
non reg.
SDRAM
10.0 ns
n/a / x8
15.0 ns
WL = 0
LVTTL
15.6 s
8.0 ns
24 ns
20 ns
Value
7.0 ns
none
page
1 / 2
= 1 CLK
128
256
x16
12
64
8
0
4
HYS64(72)V4200/8220GU
4Mx64
-10
0C
A0
8F
F0
FF
FF
80
08
04
08
01
40
00
01
70
00
80
10
00
01
04
06
01
01
00
06
80
18
14
4Mx72
-10
0C
FF
A0
8F
F0
FF
80
08
04
08
01
48
00
01
70
02
80
10
08
01
04
06
01
01
00
06
80
18
14
SDRAM-Modules
Hex
8Mx64
-10
0C
FF
02
01
A0
8F
06
06
F0
FF
80
08
04
08
40
00
70
00
80
10
00
01
04
01
01
00
80
18
14
8Mx72
-10
0C
A0
8F
06
F0
FF
FF
80
08
04
08
02
48
00
01
70
02
80
10
08
01
04
06
01
01
00
80
18
14