AM79C32A Advanced Micro Devices, AM79C32A Datasheet - Page 59

• Manufacturer Part Number: AM79C32A
• Description: Digital Subscriber Controller (DSC) Circuit
• Manufacturer: Advanced Micro Devices

DSC has no D-channel communications also in
progress.
A priority scheme is included to prevent the DSC from
dominating the bus. A new bus access will not be al-
lowed until the device detects BAC bit set to 1 in two
successive frames.
Care must be taken in use of the Bus Access Request
bit (CITDR0.7). As stated above, once access is gained
through use of this bit, the DSC will control the D and
C/I0 channels as long as it remains set. Software must
remember to clear this bit to allow other devices access.
D-Channel Arbitration
When the TIC bus feature is enabled (PPCR3.3=1), the
DLC will automatically request TIC bus access without
software intervention. The access procedure is much
the same as the C/I0 channel above.
The TIC bus control logic will check to see if the BAC
bit on the line is 0 or 1 to determine if another down-
stream device currently owns the bus. If zero, the DSC
will wait. Once a one is detected in BAC, the logic will
place the DSC's TIC bus address on the open drain
output. It will then sample this output at the IOM-2 re-
ceived data strobe point to check for conflict with other
downstream devices. If the received TIC address and
Am79C30A/32A Data Sheet
the contents of PPCR3.2-0 match, the logic will set the
BAC output to 0 indicating to other downstream de-
vices that the DSC has taken control of the D and C/I0
channels.
After is sets its BAC output to 0, the logic will compare
the TIC address on the line with PPCR3.2-0 in one
more frame to ensure ownership of the bus. If a mis-
compare occurs, the DSC will set its BAC output to 1
and return to the beginning of arbitration.
Once access is gained, the D and C/I0 channels are
the possession of the DSC. This allows the DSC to
complete D-channel communications with the Layer 1
device without interruption from other downstream de-
vices. After the DSC completes D-channel communica-
tion, logic will set the DSC's BAC bit output back to 1,
as long as the BAC request bit (CITDR0.7) is not set.
This allows other downstream devices access to the D
and C/I0 channels. If CITDR0.7=1, the device assumes
C/I0 communication is still in progress and the BAC
output remains 0 until software clears CITDR0.7.
A priority scheme is included to prevent the DSC from
dominating the bus. A new bus access will not be al-
lowed until the device detects BAC bit set to 1 in two
successive frames.
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