AM79C32A Advanced Micro Devices, AM79C32A Datasheet - Page 47

• Manufacturer Part Number: AM79C32A
• Description: Digital Subscriber Controller (DSC) Circuit
• Manufacturer: Advanced Micro Devices

D-Channel Error Register — (DER) — Read Only
The DER has the format illustrated in Table 48.
DER bits 0, 1, 3, 4, 5, and 6 are set when the last byte of the associated packet is read from the D-channel Receive
buffer.
The DER bits generate interrupts and are set/reset under the conditions shown in Table 49 (in addition to a hardware
reset).
Extended FIFO Control Register — (EFCR) — Read/Write
Address = Indirect 92H
Bit Generates Interrupt
7
0
0
0
0
0
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
Yes, if DMR2 bit 0 = 1 When seven consecutive 1s are received
Yes, if DMR2 bit 1 = 1 Upon error condition after closing flag has
Yes, if DMR2 bit 2 = 1 See section on collision detection
Yes, if DMR2 bit 3 = 1 If error occurs
Yes, if DMR2 bit 4 = 1 If error occurs
Yes, if DMR2 bit 5 = 1 If error occurs
Yes, if DMR2 bit 6 = 1 If error occurs
Yes, if DMR2 bit 7 = 1 If error occurs
6
X
X
X
X
X
X
X
X
X
X
5
Logical 1
Received Packet Abort
Non-integer number of bits have been received
Collision Detected
FCS Error
Overflow Error
Underflow Error
Overrun Error
Underrun Error
See Table 20.
X
X
X
X
X
4
Bit
X
X
X
X
X
3
Bit Set
within a packet (DSR1 bit 2 = 1)
been received
2
0
0
0
0
0
X
X
X
0
1
1
Table 48. D-Channel Error Register
X
X
X
0
0
1
Am79C30A/32A Data Sheet
Table 49. DER Interrupts
Function
Bits 7 and 2 reserved, must be written to 0
Bits 6–3 control attenuation of the analog sidetone path (ASTG)
Start of Second Received Packet In FIFO interrupt disabled
Start of Second Received Packet In FIFO interrupt enabled
Normal mode of FIFO operation
Extended mode of FIFO operation
Logical 0 (Default Value)
No abort received
Integer number of bits received
No error
No error
No error
No error
No error
No error
Bit Reset
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or when
DTCR is loaded
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or
associated DRCR
When the microprocessor reads the DER or when
DTCR is loaded
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