ISPLSI2096VL-100LT128 Lattice Semiconductor, ISPLSI2096VL-100LT128 Datasheet

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ISPLSI2096VL-100LT128

Manufacturer Part Number
ISPLSI2096VL-100LT128
Description
2.5V In-System Programmable SuperFAST High Density PLD
Manufacturer
Lattice Semiconductor
Datasheet
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
• 2.5V LOW VOLTAGE 2096 ARCHITECTURE
• HIGH PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2096vl_02
Features
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
— Interfaces with Standard 3.3V Devices (Inputs and
— 85 mA Typical Active Current
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— 2.5V In-System Programmability (ISP™) Using
— Open-Drain Output Option for Flexible Bus Interface
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Devices for Faster Prototyping
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
— PC and UNIX Platforms
Machines, Address Decoders, etc.
with ispLSI 2096V and 2096VE Devices
I/Os are 3.3V Tolerant)
f
t
Boundary Scan Test Access Port (TAP)
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
Market and Improved Product Quality
Interconnectivity
Tools, Timing Simulator and ispANALYZER™
max = 165 MHz Maximum Operating Frequency
pd = 5.5 ns Propagation Delay
2
CMOS
®
TECHNOLOGY
1
The ispLSI 2096VL is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2096VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2096VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control, and
the output drivers can source 4 mA or sink 8 mA. Each
output can be programmed independently for fast or slow
output slew rate to minimize overall output switching
Description
Functional Block Diagram
Output Routing Pool (ORP)
Output Routing Pool (ORP)
GLB
SuperFAST™ High Density PLD
Logic
Array
2.5V In-System Programmable
ispLSI
D Q
D Q
D Q
D Q
Global Routing Pool
Output Routing Pool (ORP)
Output Routing Pool (ORP)
®
(GRP)
2096VL
September 2000
0919/2096VL

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ISPLSI2096VL-100LT128 Summary of contents

Page 1

... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...

Page 2

Functional Block Diagram Figure 1. ispLSI 2096VL Functional Block Diagram I I/O 1 I/O 2 I/O 3 I I/O 6 I/O 7 I I/O 10 I/O 11 I/O 12 I/O ...

Page 3

Absolute Maximum Ratings Supply Voltage V ................................ -0.5 to +4.05V cc Input Voltage Applied ............................. -0.5 to +4.05V Off-State Output Voltage Applied .......... -0.5 to +4.05V Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...

Page 4

... Typical values are 2.5V and Maximum I varies widely with specific device configuration and operating frequency. Refer to Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum With no pull-up resistors. Specifications ispLSI 2096VL Figure 2 ...

Page 5

External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Propagation Delay Clock Frequency with Internal Feedback max f — 4 Clock Frequency ...

Page 6

Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay io t din 21 Dedicated Input Delay GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...

Page 7

Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...

Page 8

Power Consumption Power consumption in the ispLSI 2096VL device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax I CC can ...

Page 9

Pin Description NAME TQFP PIN NUMBERS I I/O 5 21, 22, 23, I I/O 11 27, 28, 29, I I/O 17 35, 36, 37, I I/O 23 41, 42, 43, I/O 24 ...

Page 10

Pin Configuration ispLSI 2096VL 128-Pin TQFP Pinout Diagram 1 I/O 85 VCC I ...

Page 11

Part Number Description ispLSI 2096VL Device Family Device Number Speed f 165 = 165 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2096VL Ordering Information FAMILY fmax (MHz) tpd (ns) 165 ispLSI 135 ...

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