L6918A STMicroelectronics, L6918A Datasheet - Page 3

• Manufacturer Part Number: L6918A
• Description: 5 BIT PROGRAMMABLE MULTIPHASE CONTROLLER
• Manufacturer: STMicroelectronics

ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
L6918A (MASTER) PIN FUNCTION
V
V
N.
10
11
12
Symbol
R
T
1
2
3
4
5
6
7
8
9
UGATE1
UGATE2
V
P
th j-amb
T
storage
Vcc, V
BOOT
MAX
max
T
V
j
Symbol
VPROG_OUT Reference voltage output used for voltage regulation.
PHASEx
SYNC_OUT
SLAVE_OK
-V
-V
-V
PHASE1
UGATE1
LGATE1
VCCDR
BOOT1
CCDR
COMP
Name
PHASE
VCC
GND
PHASE1
PHASE2
FB
Thermal Resistance Junction to Ambient
Maximum junction temperature
Storage temperature range
Junction Temperature Range
Max power dissipation at Tamb=25 C
To PGND
Boot Voltage
LGATE1, PHASE1, LGATE2, PHASE2 to PGND
VID0 to VID4
All other pins to PGND
Sustainable Peak Voltage t<20nS @ 600kHz
Channel 1 low side gate driver output.
LS Mosfet driver supply. 5V or 12V buses can be used.
This pin is connected to the Source of the upper mosfet and provides the return path for the
high side driver of channel 1.
Channel 1 high side gate driver output.
Channel 1 bootstrap capacitor pin. This pin supplies the high side driver. Connect through a
capacitor to the PHASE1 pin and through a diode to Vcc (cathode vs. boot).
Device supply voltage. The operative supply voltage is 12V.
All the internal references are referred to this pin. Connect it to the PCB signal ground.
This pin is connected to the error amplifier output and is used to compensate the control
feedback loop.
This pin is connected to the error amplifier inverting input and is used to compensate the
voltage control feedback loop.
A current proportional to the sum of the current sensed in both channel is sourced from this pin
(50 A at full load, 70 A at the Over Current threshold). Connecting a resistor R
this pin and VSEN pin allows programming the droop effect.
This pin must be connected together with the slave device VPROG_IN pin.
Filter to SGND with 1nF capacitor (a total 30nF distributed capacitance is allowed).
Synchronization output signal. From this pin exits a square - 50% duty cycle - 5Vpp –90 deg
phase shifted wave clock signal that the Slave device PLL locks to.
Connect this pin to the Slave SYNC_IN pin.
Open-drain input/output used for start-up and to manage protections as shown in the timing
diagram. Internally pulled-up. Connect together with other IC’s SLAVE_OK pin. Filter with 1nF
capacitor vs. SGND.
Parameter
Parameter
Description
-0.3 to Vcc+0.3
-0.3 to 5
-0.3 to 7
Value
-40 to 150
15
15
15
26
0 to 125
Value
150
60
2
L6918 L6918A
FB
between
Unit
C / W
Unit
V
V
V
V
V
V
V
W
C
C
C
3/35