L6918A STMicroelectronics, L6918A Datasheet - Page 26

• Manufacturer Part Number: L6918A
• Description: 5 BIT PROGRAMMABLE MULTIPHASE CONTROLLER
• Manufacturer: STMicroelectronics

L6918 L6918A
Figure 17. Device orientation (left) and sense nets routing (right).
Gate resistors of few ohms help in reducing the power dissipated by the IC without compromising the system
efficiency.
The placement of other components is also important:
Current Sense Connectio ns.
26/35
– The bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to min-
– Decoupling capacitor from Vcc and SGND placed as close as possible to the involved pins.
– Decoupling capacitor from VCCDR and PGND placed as close as possible to those pins. This capac-
– Refer to SGND all the sensible components such as frequency set-up resistor (when present) and
– Connect SGND to PGND on the load side (output capacitor) to avoid undesirable load regulation ef-
– An additional 100nF ceramic capacitor is suggested to place near HS mosfet drain. This helps in re-
– PHASE pin spikes. Since the HS mosfet switches in hard mode, heavy voltage spikes can be ob-
– Remote Buffer: The input connections for this component must be routed as parallel nets from the
– Current Reading: The Rg resistor has to be placed as close as possible to the ISENx and PGNDSx
– Moreover, when using the low side mosfet R
imize the loop that is created.
itor sustains the peak currents requested by the low-side mosfet drivers.
also the optional resistor from FB to GND used to give the positive droop effect.
fect and to ensure the right precision to the regulation when the remote sense buffer is not used.
ducing noise.
served on the PHASE pins. If these voltage spikes overcome the max breakdown voltage of the pin,
the device can absorb energy and it can cause damages. The voltage spikes must be limited by prop-
er layout, the use of gate resistors, Schottky diodes in parallel to the low side mosfets and/or snubber
network on the low side mosfets, to a value lower than 26V, for 20nSec, at Fosc of 600kHz max.
FBG/FBR pins to the load in order to compensate losses along the output power traces and also to
avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will
cause a non-optimum load regulation, increasing output tolerance.
pins in order to limit the noise injection into the device. The PCB traces connecting these resistors to
the reading point must be routed as parallel traces in order to avoid the pick-up of any common mode
noise. It's also important to avoid any offset in the measurement and to get a better precision, to con-
nect the traces as close as possible to the sensing elements, dedicated current sense resistor or low
side mosfet R
cally connected to the PHASEx pin. DO NOT CONNECT THE PINS TOGETHER AND THEN TO
THE HS SOURCE! The device won't work properly because of the noise generated by the return of
the high side driver. In this case route two separate nets: connect the PHASEx pin to the HS Source
(route together with HGATEx) with a wide net (30 mils) and the ISENx pin to the LS Drain (route to-
gether with PGNDSx). Moreover, the PGNDSx pin is always connected, through the Rg resistor, to
the PGND: DO NOT CONNECT DIRECTLY TO THE PGND! In this case the device won't work prop-
erly. Route anyway to the LS mosfet source (together with ISENx net).
Right and wrong connections are reported in Figure 18.
Symmetrical layout is also suggested to avoid any unbalance between the two phases of the converter
dsON
.
Towards HS mosfet
Towards HS mosfet
Towards LS mosfet
(30 mils wide)
(30 mils wide)
(30 mils wide)
dsON
as current sense element, the ISENx pin is practi-
To regulated output
To LS mosfet
To LS mosfet
(or sense resistor)
(or sense resistor)