UPD431000A-xxx NEC, UPD431000A-xxx Datasheet - Page 15

• Manufacturer Part Number: UPD431000A-xxx
• Description: 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT
• Manufacturer: NEC

Write Cycle Timing Chart 1 (/WE Controlled)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
I/O (Input / Output)
Address (Input)
2. Do not input data to the I/O pins while they are in the output state.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
/CE1 (Input)
CE2 (Input)
/WE (Input)
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Indefinite data out
t
AS
Data Sheet M11657EJBV0DS
t
WHZ
t
AW
t
t
CW1
CW2
t
WC
impe-
dance
High
t
WP
t
DW
Data in
t
t
WR
DH
t
OW
High
impe-
dance
Indefinite data out
PD431000A
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