M27V512-200N6TR STMicroelectronics, M27V512-200N6TR Datasheet - Page 3

• Manufacturer Part Number: M27V512-200N6TR
• Description: 512 Kbit 64Kb x8 Low Voltage UV EPROM and OTP EPROM
• Manufacturer: STMicroelectronics

Table 3. Operating Modes
Note: X = V
Table 4. Electronic Signature
Note: Outputs Q8-Q15 are set to ’0’.
The M27V800 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V800 is offered in PDIP42, SO44 and
PLCC44 package.
DEVICE OPERATION
The operating modes of the M27V800 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V
Electronic Signature.
Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Manufacturer’s Code
Device Code
Identifier
IH
Mode
or V
IL
, V
ID
= 12V
PP
V
A0
V
IH
IL
0.5V.
V
and 12V on A9 for the
IL
V
V
V
V
V
V
V
V
Pulse
E
IH
IH
IH
IL
IL
IL
IL
IL
Q7
0
1
V
V
V
V
V
V
V
V
G
X
Q6
IH
IH
IH
IL
IL
IL
IL
IL
0
0
BYTEV
Q5
1
1
V
V
V
V
V
V
V
X
X
PP
PP
PP
IH
IH
IL
IL
PP
Read Mode
The M27V800 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
signal level on the BYTEV
is at V
and the Q15A–1 pin is used for Q15 Data Output.
When the BYTEV
ganisation is selected and the Q15A–1 pin is used
for the Address Input A–1. When the memory is
logically regarded as 16 bit wide, but read in the
Byte-wide organisation, then with A–1 at V
lower 8 bits of the 16 bit data are selected and with
A–1 at V
selected.
The M27V800 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
Chip Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
from E to output (t
output after a delay of t
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
Q4
0
1
V
A9
X
X
X
X
X
X
X
X
ID
IH
IH
Q3
the Word-wide organisation is selected
0
0
the upper 8 bits of the 16 bit data are
Data Out
Data Out
Data Out
Data Out
Data In
Q0-Q7
Codes
Hi-Z
Hi-Z
Hi-Z
Q2
PP
0
0
ELQV
pin is at V
AVQV
GLQV
). Data is available at the
Q1
Data Out
Data Out
0
1
Q8-Q14
PP
Data In
) is equal to the delay
Codes
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
pin. When BYTEV
from the falling edge
IL
the Byte-wide or-
Q0
0
0
AVQV
M27V800
Data Out
Data Out
Q15A–1
Hex Data
Data In
Code
Hi-Z
Hi-Z
Hi-Z
V
V
B2h
20h
-t
IH
IL
GLQV
IL
3/16
the
PP
.