ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 41

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispClock5600 Family Data Sheet
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when
an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to
ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When
a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1uF as close to its
VCCO and GNDO pins as is practical.
BANK_[0..9]A, BANK_[0..9]B – These pins provide clock output signals. The choice of output divider (V0-V4) and
output driver type (CMOS, LVDS, SSTL, etc.) may be selected on a bank-by-bank basis. When the outputs are con-
figured as pairs of single-ended outputs, output impedance and slew rate may be selected on an output-by-output
basis.
VCCA, GNDA – These pins provide analog supply and ground for the ispClock5600 family’s internal analog cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity, it is suggested that the supply to the VCCA pin be isolated from other circuitry with a ferrite bead.
VCCD, GNDD – These pins provide digital supply and ground for the ispClock5600 family’s internal digital circuitry,
and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. to improve noise immunity it is
suggested that the supply to the VCCD pins be isolated with ferrite beads.
VCCJ – This pin provides power and a reference voltage for use by the JTAG interface circuitry. It may be set to
allow the ispClock5600 family devices to function in JTAG chains operating at voltages differing from VCCD.
REFA+, REFA-, REFB+, REFB- – These input pins provide the inputs for clock signals, and can accommodate
either single ended or differential signal protocols by using either just the ‘+’ pins, or both the ‘+’ and ‘-‘ pins. Two
sets of inputs are provided to accommodate the use of different signal sources and redundant clock sources.
REFSEL – This input pin is used to select which clock input pair (REFA+/- or REB+/-) is selected for use as the ref-
erence input. When REFSEL=0, REFA+/- is used, and when REFSEL=1, REFB+/- is used.
REFVTT – This pin is used to provide a termination voltage for the reference inputs when they are configured for
SSTL or HSTL logic, and should be connected to a suitable voltage supply in those cases.
FBKA+, FBKA-, FBKB+, FBKB- – These input pins provide the inputs for feedback sense of output clock signals,
and can accommodate either single ended or differential signal protocols by using either just the ‘+’ pins, or both
the ‘+’ and ‘-‘ pins. Two sets of inputs are provided to accommodate the use of alternate feedback signal sources.
FBKSEL – This input pin is used to select which clock input pair (FBKA+/- or FBK+/-) is selected for use as the
feedback input. When FBKSEL=0, FBKA+/- is used, and when FBKSEL=1, FBKB+/- is used.
FBKVTT – This pin is used to provide a termination voltage for the feedback inputs when they are configured for
SSTL or HSTL logic, and should be connected to a suitable voltage supply in those cases.
TDO, TDI, TCK, TMS – These pins comprise the ispClock5600 device’s JTAG interface. The signal levels for these
pins are determined by the selection of the VCCJ voltage.
LOCK – This output pin indicates that the device’s PLL is in a locked condition when it goes low.
SGATE – This input pin provides a synchronous gating function for the outputs, which may be enabled on a bank-
by-bank basis. When the synchronous gating function is enabled for a given bank, that bank’s outputs will output a
clock signal when the SGATE pin is HIGH, and will drive a constant HIGH or LOW when the SGATE pin is LOW.
Synchronous gating ensures that when the state of SGATE is changed, no partial clock pulses will appear at the
outputs.
OEX, OEY – These pins are used to enable the outputs or put them into a high-impedance condition. Each output
may be set so that it is always on, always off, enabled by OEX or enabled by OEY.
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