ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 32

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
ispClock5600 Family Data Sheet
When the ispClock5600 begins operating from initial power-on, the VCO starts running at a very low frequency
(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being
applied to the rest of the system, it is recommended that either the SGATE, OEX, or OEY pins be used to control
the outputs based on the status of the LOCK pin. Holding the SGATE pin LOW during power-up will result in the
BANK outputs being asserted HIGH or LOW (depending on inversion status) until SGATE is brought HIGH. Assert-
ing OEX or OEY high will result in the BANK outputs being held in a high-impedance state until the OEX or OEY
pin is pulled LOW. One should not use the GOE pin to control the outputs in anticipation of LOCK status, as holding
GOE HIGH also disables internal feedback and will prevent the device from ever achieving lock.
Software-Based Design Environment
Designers can configure the ispClock5600 using Lattice’s PAC-Designer software, an easy to use, Microsoft Windows
compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environ-
ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to
the serial programming interface pins of the ispClock5600. A library of configurations is included with basic solutions
and examples of advanced circuit techniques are available on the Lattice web site at www.latticesemi.com. In addi-
tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation.
The PAC-Designer schematic window, shown in Figure 28 provides access to all configurable ispClock5600 elements
via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such
as power, ground and the serial digital interface are omitted for clarity. Any element in the schematic window can be
accessed via mouse operations as well as menu commands. When completed, configurations can be saved and
downloaded to devices.
Figure 28. PAC-Designer Design Entry Screen
In-System Programming
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The ispClock5600 is an In-System Programmable (ISP™) device. This is accomplished by integrating all E
CMOS
configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG
interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in
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non-volatile E
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispClock5600 instruc-
tions are described in the JTAG interface section of this data sheet.
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