ISPPAC-CLK5610V-01T100C LATTICE [Lattice Semiconductor], ISPPAC-CLK5610V-01T100C Datasheet - Page 15

• Manufacturer Part Number: ISPPAC-CLK5610V-01T100C
• Description: In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
match. The option of which mode to use is programmable and may be set using PAC-Designer software (available
from the Lattice web site at www.latticesemi.com).
In phase-lock mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. In fre-
quency-lock mode, however, the PLL must be in a locked condition for a set number of phase detector cycles
before the LOCK signal will be asserted. The number of cycles required before asserting the LOCK signal in fre-
quency-lock mode can be set from 16 through 256.
When the lock condition is lost the LOCK signal will be de-asserted immediately in both phase-lock and frequency-
lock detection modes. In frequency-lock mode, however, if the input reference signal is stopped, the LOCK output
may continue to be asserted. In phase-lock mode, a loss of the input reference signal will always result in de-asser-
tion of the LOCK output.
Loop Filter
A simplified schematic for the ispClock5600 loop filter is shown in Figure 11. The filter’s capacitors are fixed, and
the response is controlled by setting the value of the phase-detector’s output current source’s and the value of the
variable resistor. The phase detector output current has 14 possible settings, ranging from 3µA to 55µA, while the
resistor may be set to any one of six values ranging from 2.3K to 9.3K. This provides a total of 84 unique I-R com-
binations which may be selected.
Figure 11. ispClock5600 Loop Filter (Simplified)
Because the selection of an optimal PLL loop filter can be a daunting task, PAC-Designer offers a set of default fil-
ter settings which will provide acceptable performance for most applications. The primary criterion for selecting one
of these settings is the total division factor used in the feedback path, or the ratio between the VCO output fre-
quency and the frequency output by the N feedback divider (N x V
conditions under which they should be used.
M-divider
N-divider
From
From
Phase Detector
I
I
15
C
feedback
1
ispClock5600 Family Data Sheet
). Table 2 lists these default settings and
R
C
2
To VCO