ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 25

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 22b shows another derating curve, derived under the assumption that the output frequency is 100MHz. For
many applications, 100MHz outputs will be a more realistic scenario. Comparing the maximum temperature limits
of Figure 22b with Figure 22a, one can see that significantly higher operating temperatures are possible in LVC-
MOS 3.3V output mode with more outputs at 100MHz than at 320MHz.
The examples above described examples using LVCMOS 3.3V logic, which represents the maximum power dissi-
pation case at higher frequencies. For optimal operation at very high frequencies (> 150 MHz) LVDS will often be
the best choice from a signal integrity standpoint. For LVDS-configured outputs, the maximum ICCO current con-
sumption per bank is low enough that both the ispClock5510 and ispClock5520 can operate all outputs at maxi-
mum frequency over their complete rated temperature range, as shown in Figure 22c.
Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced
airflow present in a given design, actual die operating temperature is subject to considerable variation from that
which may be theoretically predicted from package characteristics and device power dissipation.
Output Enable Controls
The ispClock5500 family provides the user with several options for enabling and disabling output pins, as well as
suspending the output clock. In addition to providing the user with the ability to reduce the device’s power con-
sumption by turning off unused drivers, these features can also be used for functional testing purposes. The follow-
ing inputs pins are used for output enable functions:
Additionally, internal E
external control pins.
When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal configuration. When
GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled
by the OEX and OEY pins. Internal E
enabled (when GOE pin is LOW), never enabled (permanently off), or selectively enabled by the state of either
OEX or OEY. Bringing GOE high will also disable the internal feedback driver and will result in a loss of lock.
Synchronous output gating is provided by ispClock5500 devices through the use of the SGATE pin. The SGATE pin
does not disable the output driver, but merely forces the output to either a high or low state, depending on the out-
put driver’s polarity setting. If the output driver polarity is true, the output will be forced LOW when SGATE is
brought LOW, while if it is inverted, the output will be forced HIGH. A primary feature of the SGATE function is that
the clock output is enabled and disabled synchronous to the selected internal clock source. This prevents the gen-
eration of partial, ‘runt’, output clock pulses, which would otherwise occur with simple combinatorial gating
schemes. The SGATE is available to all clock outputs and is selectable on a pin-by-pin basis.
Table 5 shows the behavior of the outputs for various combinations of the output enables, SGATE input, and
E
Table 5. Clock Output Enable Functions
2
CMOS configuration.
• GOE – global output enable
• OEX, OEY – secondary output enable controls
• SGATE – synchronous output control
2
CMOS configuration bits are provided for the purpose of modifying the effects of these
GOE
X
0
0
0
0
0
1
OEX
X
X
X
X
X
0
1
2
CMOS configuration is used to establish whether the output driver is always
OEY
X
X
X
X
X
0
1
E
Enable on OEX
Enable on OEX
Enable on OEY
Enable on OEY
2
Always OFF
Configuration
Always ON
25
n/a
ispClock5500 Family Data Sheet
Clock Out
Clock Out
Clock Out
Output
High-Z
High-Z
High-Z
High-Z