ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 16

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
The choice of loop filter parameters can have significant effects on settling time, output jitter, and whether the PLL
will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2 were
chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that when
the skew mode is set to ‘coarse’, the effective value of NxV must be doubled. Refer to the section titled ‘Coarse
Skew Mode’ on page 26 for more details.
VCO
The ispClock5500 provides an internal VCO which provides an output frequency ranging from 320MHz to 640MHz.
The VCO is implemented using differential circuit design techniques which minimize the influence of power supply
noise on measured output jitter. The VCO is also used to generate skews as a function of the total VCO period.
Using the VCO as the basis for controlling output skew allows for highly precise and consistent skew generation,
both from device-to-device, as well as channel-to-channel within the same device.
M, N, and V Dividers
The ispClock5500 incorporates a set of programmable dividers which provide the ability to synthesize output fre-
quencies differing from that of the reference clock input.
The input, or M, divider prescales the input reference frequency, and can be programmed with integer values over
the range of 1 to 32. To achieve low levels of output jitter, it is best to use the smallest M divider value possible.
The feedback, or N, divider prescales the feedback frequency and like the M divider, can also be programmed with
integer values ranging from 1 to 32.
Each one of the five output, or V, dividers can be independently programmed to provide even division ratios ranging
from 2 to 64.
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f
culated as:
where
Note that because the feedback may be taken from any V divider, V
Because the VCO has an operating frequency range spanning 320 MHz to 640 MHz, and the V dividers provide
division ratios from 2 to 64, the ispClock5500 can generate output signals ranging from 5MHz to 320 MHz. For per-
formance and stability reasons, however, there are several constraints which should be followed when selecting
divider values:
Output Duty Cycle
The ispClock5500’s output duty cycle varies as a function of the V divider used to generate that output. Table 3
shows the nominal output duty cycle as a function of the V divider setting. Note that if the output is inverted, the
duty cycle will be equal to 100%-DC%, where DC% is the duty cycle indicated in the table. For example, with a V-
divider of 6, the non-inverted duty cycle from Table 3 will be 67%. For an inverted output, the duty cycle will be
100%-67% or 33%.
f
f
M and N are the input and feedback divider settings
V
V
• Use the smallest feasible value for the M divider
• The output frequency from the M (and N) divider should be greater or equal to 10 MHz.
• The product of the N divider and the V divider used to close the PLL’s feedback loop should be less than or
k
ref
fbk
k
equal to 64 (N x V
is the frequency of V divider k
is the setting of the V divider used to provide output k
is the input reference frequency
is the setting of the V divider used to close the PLL feedback path
fbk
≤ 64)
f
k
=
f
ref
16
N x V
M x V
fbk
k
k
and V
ispClock5500 Family Data Sheet
fbk
may refer to the same divider.
k
) may be cal-
(1)