ISPPAC-CLK5510V LATTICE [Lattice Semiconductor], ISPPAC-CLK5510V Datasheet - Page 18

• Manufacturer Part Number: ISPPAC-CLK5510V
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 12. ispClock5500 Clock Reference Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left floating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 13 shows the proper
configuration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate configuration setting for this particular standard.
Figure 13. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
V
shows an appropriate configuration. Refer to the “Recommended Operating Conditions - Supported Logic Stan-
dards” table in this data sheet for suitable values of V
TT
termination supply. The positive input’s terminating resistor should be engaged and set to 50Ω. Figure 14
REFVTT
REFA+
REFA-
ispClock5500
R
T
Signal In
No Connect
No Connect
REFVTT
REFA+
REFA-
R
T
ispClock5500
R
T
OPEN
REF
Single-ended
Differential
18
Receiver
Receiver
and V
ref
value, and the REFVTT terminal should be tied to a
TT.
ispClock5500 Family Data Sheet
Single-ended
Receiver
To Internal
Logic