XR16C2450IJ EXAR [Exar Corporation], XR16C2450IJ Datasheet - Page 17

• Manufacturer Part Number: XR16C2450IJ
• Description: 2.97V TO 5.5V DUART
• Manufacturer: EXAR [Exar Corporation]

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REV. 1.0.0
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
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The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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MCR[2]: Reserved
OP1# is not available as an output pin on the 2450. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
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MCR[4]: Internal Loopback Enable
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MCR[7:5]: Reserved
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
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LSR[1]: Receiver Overrun Flag
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4.6
4.7
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register .
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error. An interrupt will be
generated immediately if LSR interrupt is enabled (IER bit-2).
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
Line Status Register (LSR) - Read Only
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Figure
7.
2.97V TO 5.5V DUART
XR16C2450