DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 60

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6010
FIGURE 9-1:
9.1
The 16-bit timer can be placed in the Gated Time Accu-
mulation mode. This mode allows the internal T
increment the respective timer when the gate input sig-
nal (T1CK pin) is asserted high. Control bit TGATE
(T1CON<6>) must be set to enable this mode. The
timer must be enabled (TON = 1) and the timer clock
source set to internal (TCS = 0).
When the CPU goes into the Idle mode, the timer will
stop incrementing, unless TSIDL = 0. If TSIDL = 1, the
timer will resume the incrementing sequence upon
termination of the CPU Idle mode.
9.2
The input clock (F
Timer, has a prescale option of 1:1, 1:8, 1:64, and
1:256
(T1CON<5:4>). The prescaler counter is cleared when
any of the following occurs:
• a write to the TMR1 register
• clearing of the TON bit (T1CON<15>)
• device Reset such as POR and BOR
However, if the timer is disabled (TON = 0), then the
timer prescaler cannot be reset since the prescaler
clock is halted.
TMR1 is not cleared when T1CON is written. It is
cleared by writing to the TMR1 register.
DS70119D-page 58
selected
Timer Gate Operation
Timer Prescaler
SOSCO/
SOSCI
T1IF
Event Flag
T1CK
OSC
by
/4 or external clock) to the 16-bit
16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER)
control
TGATE
0
1
Reset
Equal
bits
LPOSCEN
Comparator x 16
TCKPS<1:0>
TMR1
PR1
CY
Preliminary
to
Q
Q
Gate
Sync
CK
T
D
CY
9.3
During CPU Sleep mode, the timer will operate if:
• The timer module is enabled (TON = 1) and
• The timer clock source is selected as external
• The TSYNC bit (T1CON<2>) is asserted to a logic
When all three conditions are true, the timer will con-
tinue to count up to the period register and be reset to
0x0000.
When a match between the timer and the period regis-
ter occurs, an interrupt can be generated, if the
respective Timer Interrupt Enable bit is asserted.
TGATE
(TCS = 1) and
0, which defines the external clock source as
asynchronous
Timer Operation During Sleep
Mode
1 X
0 0
0 1
TON
(3)
TSYNC
 2004 Microchip Technology Inc.
0
1
1, 8, 64, 256
TCKPS<1:0>
Prescaler
Sync
2