DSPIC30F6010 MICROCHIP [Microchip Technology], DSPIC30F6010 Datasheet - Page 132

• Manufacturer Part Number: DSPIC30F6010
• Description: High-Performance Digital Signal Controllers
• Manufacturer: MICROCHIP [Microchip Technology]

dsPIC30F6010
20.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to 5 alternate sources of
conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
20.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an auto
start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multi-channel group conversion sequence.
DS70119D-page 130
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the A/D at the maximum spec-
ified conversion speed, the Auto Convert
Trigger option should be selected (SSRC
= 111) and the Auto Sample Time bits
shoud be set to 1 T
This configuration will give a total conver-
sion period (sample + convert) of 13 T
The use of any other conversion trigger
will result in additional T
synchronize the external event to the A/D.
AD
(SAMC = 00001).
AD
cycles to
AD
wait is
AD
Preliminary
.
20.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a six
bit counter. There are 64 possible options for T
EQUATION 20-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 154 nsec (for V
Specifications section for minimum T
operating conditions.
Example 20-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 20-1:
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 9
Selecting the A/D Conversion
Clock
ADCS<5:0> = 2
Minimum T
T
Actual T
AD
ADCS<5:0> = 2
= T
CY
AD
T
DD
AD
CY
* (0.5*(ADCS<5:0> +1))
= 2 •
= 8.33
=
=
= 165 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 5V). Refer to the Electrical
= 154 nsec
= 33 nsec (30 MIPS)
 2004 Microchip Technology Inc.
T
33 nsec
T
T
CY
2
AD
CY
154 nsec
2
33 nsec
(ADCS<5:0> + 1)
T
T
– 1
AD
CY
AD
(9 + 1)
. The source of the
– 1
– 1
AD
under other
AD
AD
.
time