HIP6502BEVAL1 INTERSIL [Intersil Corporation], HIP6502BEVAL1 Datasheet

HIP6502BEVAL1

Manufacturer Part Number

HIP6502BEVAL1

Description

Multiple Linear Power Controller with ACPI Control Interface

Manufacturer

INTERSIL [Intersil Corporation]

Datasheet

1.HIP6502BEVAL1.pdf (14 pages)

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Multiple Linear Power Controller with

ACPI Control Interface

The HIP6502B complements either an HIP6020 or an

HIP6021 in ACPI-compliant designs for microprocessor and

computer applications. The IC integrates four linear

controllers/regulators, switching, monitoring and control

functions into a 20-pin SOIC package. One linear controller

generates the 3.3V

supply’s 5VSB output, powering the south bridge and the

PCI slots through an external pass transistor during sleep

states (S3, S4/S5). A second transistor is used to switch in

the ATX 3.3V output for operation during S0 and S1/S2

(active) operating states. Two linear controllers/regulators

supply at choice either or both of the computer system’s

2.5V or 3.3V memory power through external pass

transistors in active states. During sleep states, integrated

pass transistors supply the sleep power. Another controller

powers up the 5V

output in active states, and the ATX 5VSB in sleep states.

One internal regulator outputs a dedicated, noise-free 2.5V

clock chip supply. The HIP6502B’s operating mode (active

outputs or sleep outputs) is selectable through two digital

control pins, S3 and S5. Enabling sleep state support on the

state, the 3.3V

external N-channel pass MOSFETs to connect the outputs

directly to the 3.3V input supplied by an ATX (or equivalent)

power supply, for minimal losses. In sleep state, power

delivery on both outputs is transferred to NPN transistors -

external to the controller on the 3.3V

3.3V

performed through an external NPN transistor. In sleep

state, conduction on this output is transferred to an internal

pass transistor. The 5V

external MOS transistors. In sleep states, a PMOS (or PNP)

transistor conducts the current from the ATX 5VSB output;

while in active state, current ﬂow is transferred to an NMOS

transistor connected to the ATX 5V output. The operation of

the 5V

S3 and S5 pins, but that of the EN5VDL pin as well. The

3.3V

5VSB voltage is applied to the chip. The 2.5V

only active during S0 and S1/S2, and uses the 3V3 pin as

input source for its internal pass element.

Ordering Information

HIP6502BCB

HIP6502BEVAL1

PART NUMBER

DUAL

MEM

DUAL

output is offered through the EN5VDL pin. In active

. Active state regulation on the 2.5V

/3.3V

output is dictated not only by the status of the

DUAL

output is active for as long as the ATX

DUAL

Evaluation Board

RANGE (

and 3.3V

TEMP.

0 to 70

DUAL

plane by switching in the ATX 5V

/3.3V

output is powered through two

MEM

voltage plane from the ATX

20 Ld SOIC

linear regulators use

1-888-INTERSIL or 321-724-7143

Data Sheet

DUAL

PACKAGE

, internal on the

MEM

CLK

output is

M20.3

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil and Design is a trademark of Intersil Corporation.

Features

• Provides 5 ACPI-Controlled Voltages

• Excellent Output Voltage Regulation

• Small Size

• Dual Memory Voltage Support Via MSEL Pin

• Under-Voltage Monitoring of All Outputs with Centralized

Applications

• Motherboard Power Regulation for ACPI-Compliant

Pinout

- 5V

- 3.3V

- 2.5V

- 3.3V

- 2.5V

- 3.3V

- 2.5V

- Very Low External Component Count

- 2.5V for RDRAM Memory

- 3.3V for SDRAM Memory

- Both 2.5V and 3.3V for Flexible Systems

FAULT Reporting and Temperature Shutdown

Computers

Sleep State Only

Temperature; Both Operational States (3.3V

Sleep Only)

DUAL

MEM

CLK

DUAL

MEM

CLK

3V3DLSB

EN5VDL

USB/Keyboard/Mouse (Active/Sleep)

Clock/Processor Terminations (Active Only)

Output: 2.0% Over Temperature

VSEN2

VSEN1

3V3DL

May 2000

/3.3V

RDRAM (Active/Sleep)

SDRAM (Active/Sleep)

/3.3V

and 3.3V

VCLK

5VSB

3V3

PCI/Auxiliary/LAN (Active/Sleep)

Output: 2.0% Over Temperature;

MEM

TOP VIEW

HIP6502B

(SOIC)

Output: 2.0% Over

File Number

MSEL

5VDL

5VDLSB

DLA

FAULT

HIP6502B

DRV2

12V

GND

Intersil Corporation 2000

MEM

4871

Related parts for HIP6502BEVAL1

HIP6502BEVAL1 Summary of contents

Page 1

... The 2.5V only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element. Ordering Information TEMP. o PART NUMBER RANGE ( C) PACKAGE HIP6502BCB SOIC HIP6502BEVAL1 Evaluation Board 1 1-888-INTERSIL or 321-724-7143 Features • Provides 5 ACPI-Controlled Voltages - 5V DUAL - 3.3V DUAL - 2.5V MEM - 3.3V MEM - 2 ...

Page 2

Block Diagram 12V 12V MONITOR 10.8V/9.8V TO 5VSB EA3 + - TO UV DETECTOR VSEN1 FAULT UV DETECTOR - + + UV COMPARATOR 3.75V - 5VDL GND 3V3DL 5V 3V3 3V3DLSB 5V MONITOR 4.5V/4.25V EA4 - + 3V3 MONITOR 2.97V/2.8V ...

Page 3

Simpliﬁed Power System Diagram +5V IN +12V IN +5V SB +3. 3.3V MEM 3. 3.3V /3.3V DUAL SB 3.3V FAULT MSEL SHUTDOWN SX 2 EN5VDL Typical Application +5V IN +12V IN +5V SB +3. ...

Page 4

Absolute Maximum Ratings Supply Voltage +7.0V 5VSB 12V. . ...

Page 5

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued) PARAMETER DRV2 Output Drive Current 3.3V /3.3V LINEAR REGULATOR (V DUAL SB Sleep State Regulation 3V3DL Nominal Voltage Level 3V3DL Undervoltage Rising Threshold 3V3DL ...

Page 6

Functional Pin Descriptions 3V3 (Pin 7) Connect this pin to the ATX 3.3V output. This pin provides the output current for the 2V5CLK pin, and is monitored for power quality. 5VSB (Pin 2) Provide a very well de-coupled 5V bias ...

Page 7

VSEN1 (Pin 3) Connect this pin to the 3.3V memory output (V sleep states, this pin is regulated to 3.3V through an internal pass transistor capable of delivering 300mA (typically). The active-state voltage at this pin is provided from the ...

Page 8

S3 S5 3.3V, 5V, 12V 3V3DLSB DLA 3V3DL 5VDLSB 5VDL FIGURE 5. 5V TIMING DIAGRAM FOR EN5VDL = 0; DUAL 3V /3V DUAL SB Not shown in these diagrams is the deglitching feature used to protect against false sleep ...

Page 9

SOFT-START INTO ACTIVE STATES (S0, S1) If both S3 and S5 are logic high at the time the 5VSB is applied, the HIP6502B will assume active state wake-up and keep off the controlled external transistors and the VCLK output until ...

Page 10

Operation resumes at 140 temperature cycling occurs until the fault-causing condition is removed. In HIP6502B applications, loss of any one active ATX output (3. 12V ; as detected by the on-board ...

Page 11

Minimize any leakage current paths from SS node, since the internal current source is only 10 A. +12V IN + 5VSB 12V 12V 5VSB SS 5VDLSB HF1 5VDL C ...

Page 12

ATX’s outputs and the HIP6502B’s regulation levels could have as a result a brisk transfer of energy from the input capacitors to the supplied outputs. At the transition between active and sleep states, this phenomena ...

Page 13

HIP6502B Application Circuit Figure 11 shows an application circuit of an ACPI- sanctioned power management system for a microprocessor computer system. The power supply provides the 3.3V /3.3V voltage (V ), the SDRAM 3.3V DUAL SB OUT3 voltage (V ), ...

Page 14

Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - - 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the “MO ...

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