MC68HC11F1CPU2 FREESCALE [Freescale Semiconductor, Inc], MC68HC11F1CPU2 Datasheet - Page 88

• Manufacturer Part Number: MC68HC11F1CPU2
• Description: MC68HC11F1 Technical Data
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

7.3 Receive Operation
7-2
REQUESTS
TRANSMITTER
During receive operations, the transmit sequence is reversed. The serial shift register
receives data and transfers it to a parallel receive data register (SCDR) as a complete
word. This double buffered operation allows a character to be shifted in serially while
another character is already in the SCDR. An advanced data recovery scheme distin-
guishes valid data from noise in the serial data stream. The data input is selectively
sampled to detect receive data, and a majority voting circuit determines the value and
integrity of each bit.
BAUD RATE
SCI Rx
CLOCK
SCCR1 SCI CONTROL 1
SCI INTERRUPT
REQUEST
H (8) 7 6 5 4 3 2 1 0
10 (11) - BIT Tx SHIFT REGISTER
Figure 7-1 SCI Transmitter Block Diagram
Freescale Semiconductor, Inc.
SCDR Tx BUFFER
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
TDRE
TIE
TC
TCIE
CONTROL LOGIC
Go to: www.freescale.com
TRANSMITTER
SCSR INTERRUPT STATUS
L
(WRITE-ONLY)
SCCR2 SCI CONTROL 2
DIRECTION (OUT)
FORCE PIN
8
AND CONTROL
PIN BUFFER
8
DDD1
INTERNAL
DATA BUS
8
8
TECHNICAL DATA
MC68HC11F1
PD1/
TxD