MC68HC11F1CPU2 FREESCALE [Freescale Semiconductor, Inc], MC68HC11F1CPU2 Datasheet - Page 68

• Manufacturer Part Number: MC68HC11F1CPU2
• Description: MC68HC11F1 Technical Data
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.2.6 Pulse Accumulator
5.2.7 Computer Operating Properly (COP)
5.2.8 Serial Communications Interface (SCI)
5.2.9 Serial Peripheral Interface (SPI)
5.2.10 Analog-to-Digital Converter
5.2.11 System
5.3 Reset and Interrupt Priority
5-6
The pulse accumulator system is disabled at reset so that the pulse accumulator input
(PAI) pin defaults to being a general-purpose input pin.
The COP watchdog system is enabled if the NOCOP control bit in the CONFIG regis-
ter is cleared, and disabled if NOCOP is set. The COP rate is set for the shortest du-
ration time-out.
The reset condition of the SCI system is independent of the operating mode. All trans-
mit and receive interrupts are masked and both the transmitter and receiver are dis-
abled so the port pins default to being general-purpose I/O lines. The SCI frame format
is initialized to an 8-bit character size. The send break and receiver wakeup functions
are disabled. The TDRE and TC status bits in the SCI status register are both set, in-
dicating that there is no transmit data in either the transmit data register or the transmit
serial shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status
bits are cleared.
The SPI system is disabled by reset. The port pins associated with this function default
to being general-purpose I/O lines.
The A/D converter configuration is indeterminate after reset. The ADPU bit is cleared
by reset, which disables the A/D system. The conversion complete flag is cleared by
reset.
The EEPROM programming controls are disabled, so the memory system is config-
ured for normal read operation. PSEL[3:0] are initialized with the binary value %0101,
causing the external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin is
configured for level-sensitive operation (for wired-OR systems). The RBOOT, SMOD,
and MDA bits in the HPRIO register reflect the status of the MODB and MODA inputs
at the rising edge of reset. The DLY control bit is set to specify that an oscillator start-
up delay is imposed upon recovery from STOP mode. The clock monitor system is dis-
abled because CME and FCME are cleared.
Resets and interrupts have a hardware priority that determines which reset or interrupt
is serviced first when simultaneous requests occur. Any maskable interrupt can be giv-
en priority over other maskable interrupts.
The first six interrupt sources are not maskable. The priority arrangement for these
sources is as follows:
Freescale Semiconductor, Inc.
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RESETS AND INTERRUPTS
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TECHNICAL DATA
MC68HC11F1