DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 62

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

D0-D6
D7
5 0 Registers
5 18 STATE THRESHOLD REGISTER (STR)
The State Threshold Register contains the start value for the State Timer This timer is used in conjunction with the State
Prescale Timer to count the Line State duration The State Timer will decrement every 80 ns if the State Prescale Timer is zero
and the current Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect The State
Timer takes
to reach zero during a continuous line state condition
The threshold values for the State Timer and State Prescale Timer are simultaneously loaded into both counters if one of the
following conditions is true
1 Both the State Timer and State Prescale Timer reach zero and the current Line State is Halt Line State Idle Line State
or
2 A line state change occurs and the new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or
or
3 The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle
In addition the value of the State Prescale Threshold Register is loaded into the State Prescale Counter if the State Prescale
Timer reaches zero
The State Timer and State Prescale Timer will reset by reloading the threshold values if a Line State change occurs and the
new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect On detection of ALS
NLS or LSU the timer will not decrement
ACCESS RULES
Bit
Master Line State Quiet Line State or No Signal Detect
No Signal Detect
RES
D7
ADDRESS
ST0-ST6
RES
Symbol
11h
ST6
D6
STATE THRESHOLD BIT
ST0 is the Least Significant Bit (LSB)
RESERVED Reserved for future use
Note Users are discouraged from using this bit Write data is ignored since the reserved bit is permanently set to 0
(Continued)
Always
READ
ST5
D5
ST4
((SPTR
k
D4
WRITE
Always
0-6
l
a
Start value for the State Timer
1) x STR
ST3
D3
62
a
SPTR) x 80 ns
Description
ST2
D2
ST1
D1
ST0
D0