DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 73

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.4 Configuring Interrupts
DSP56303 interrupt handling, like that for all DSP56300 family members, is optimized for DSP
applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture
Overview, in the DSP56300 Family Manual. Two registers are programmed to configure the
interrupt characteristics:
The interrupt table resides in the 256 locations of program memory to which the PCU vector base
address (VBA) register points. These locations store the starting instructions of the interrupt
handler for each specified interrupt. The memory is programmed by the bootstrap program at
start-up.
4.4.1 Interrupt Priority Registers (IPRC and IPRP)
There are two interrupt priority registers in the DSP56303. The IPRC (Figure 4-3) is dedicated to
DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to DSP56303 peripheral
interrupt sources.
Freescale Semiconductor
Interrupt Priority Register-Core (IPRC). Configure the priority levels for the core DMA
interrupts and the external interrupt lines as well as the interrupt line trigger modes.
Interrupt Priority Register-Peripherals (IPRP). Configure the priority levels for the
interrupts used with the internal peripheral devices
D5L1
IDL2
23
11
Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)
D5L0
IDL1 IDL0
22
10
D4L1
21
9
D4L0
ICL2
20
8
D3L1
ICL1
19
7
DSP56303 User’s Manual, Rev. 2
D3L0
ICL0
18
6
D2L1
IBL2
17
5
D2L0
IBL1
16
4
D1L1
IBL0
15
3
D1L0
IAL2
14
2
D0L1
IAL1
13
1
D0L0
IAL0
12
0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
Configuring Interrupts
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