DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 150

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Enhanced Synchronous Serial Interface (ESSI)
corresponding SC (or
CRB bits are cleared by either a hardware
7-18
Bit Number
23
22
21
20
19
18
Bit Name
REIE
TEIE
RLIE
TLIE
RIE
TIE
Table 7-4. ESSI Control Register B (CRB) Bit Definitions
STD
Reset Value
in the case of TX0) signal remains in a high-impedance state. The
0
0
0
0
0
0
DSP56303 User’s Manual, Rev. 2
Receive Exception Interrupt Enable
When the REIE bit is set, the DSP is interrupted when both RDF and ROE
in the ESSI status register are set. When REIE is cleared, this interrupt is
disabled. The receive interrupt is documented in
followed by a read of the receive data register clears both ROE and the
pending interrupt.
Transmit Exception Interrupt Enable
When the TEIE bit is set, the DSP is interrupted when both TDE and TUE in
the ESSI status register are set. When TEIE is cleared, this interrupt is
disabled. The use of the transmit interrupt is documented
in Section 7.3.3, Exceptions, on page 7-7. A read of the status register,
followed by a write to all the data registers of the enabled transmitters,
clears both TUE and the pending interrupt.
Receive Last Slot Interrupt Enable
Enables/disables an interrupt after the last slot of a frame ends when the
ESSI is in Network mode. When RLIE is set, the DSP is interrupted after the
last slot in a frame ends regardless of the receive mask register setting.
When RLIE is cleared, the receive last slot interrupt is disabled. The use of
the receive last slot interrupt is documented in
in On-Demand mode (DC = $0).
Transmit Last Slot Interrupt Enable
Enables/disables an interrupt at the beginning of the last slot of a frame
when the ESSI is in Network mode. When TLIE is set, the DSP is
interrupted at the start of the last slot in a frame regardless of the transmit
mask register setting. When TLIE is cleared, the transmit last slot interrupt
is disabled. The transmit last slot interrupt is documented
in Section 7.3.3, Exceptions, on page 7-7. TLIE is disabled when the ESSI
is in On-Demand mode (DC = $0).
Receive Interrupt Enable
Enables/disables a DSP receive data interrupt; the interrupt is generated
when both the RIE and receive data register full (RDF) bit (in the SSISR)
are set. When RIE is cleared, this interrupt is disabled. The receive interrupt
is documented in Section 7.3.3, Exceptions, on page 7-7. When the
receive data register is read, it clears RDF and the pending interrupt.
Receive interrupts with exception have higher priority than normal receive
data interrupts. If the receiver overrun error (ROE) bit is set (signaling that
an exception has occurred) and the REIE bit is set, the ESSI requests an
SSI receive data with exception interrupt from the interrupt controller.
Transmit Interrupt Enable
Enables/disables a DSP transmit interrupt; the interrupt is generated when
both the TIE and the TDE bits in the ESSI status register are set. When TIE
is cleared, the transmit interrupt is disabled. The transmit interrupt is
documented in Section 7.3.3. When data is written to the data registers of
the enabled transmitters or to the TSR, it clears TDE and also clears the
interrupt. Transmit interrupts with exception conditions have higher priority
than normal transmit data interrupts. If the transmitter underrun error (TUE)
bit is set (signaling that an exception has occurred) and the TEIE bit is set,
the ESSI requests an SSI transmit data with exception interrupt from the
interrupt controller.
Section 7.3.3, Exceptions, on page 7-7. A read of the status register
Section 7.3.3, Exceptions, on page 7-7. RLIE is disabled when the ESSI is
RESET
signal or a software RESET instruction.
Description
Freescale Semiconductor