DSP56303 FREESCALE [Freescale Semiconductor, Inc], DSP56303 Datasheet - Page 31

• Manufacturer Part Number: DSP56303
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

2.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After
Freescale Semiconductor
BR
BG
BB
CAS
BCLK
BCLK
Signal
Name
Output
Input
Input/
Output
Output
Output
Output
Type
Output
(deasserted)
State during Stop/Wait
depends on the BRH
bit setting:
• BRH = 0: Output,
• BRH = 1: Maintains
Ignored Input
Ignored Input
Tri-stated
Tri-stated
Tri-stated
Table 2-8. External Bus Control Signals (Continued)
State During Reset,
RESET
deasserted.
last state (that is, if
asserted, remains
asserted)
Stop, or Wait
is deasserted, these inputs are hardware interrupt request lines.
DSP56303 User’s Manual, Rev. 2
Bus Request
Asserted when the DSP requests bus mastership and deasserted when
the DSP no longer needs the bus. BR can be asserted or deasserted
independently of whether the DSP56303 is a bus master or a bus slave.
Bus “parking” allows BR to be deasserted even though the DSP56303 is
the bus master (see the description of bus “parking” in the BB signal
description). The Bus Request Hold (BRH) bit in the BCR allows
asserted under software control, even though the DSP does not need the
bus. BR is typically sent to an external bus arbitrator that controls the
priority, parking and tenure of each master on the same external bus. BR
is affected only by DSP requests for the external bus, never for the
internal bus. During hardware reset, BR is deasserted and the arbitration
is reset to the bus slave state.
Bus Grant
Must be asserted/deasserted synchronous to CLKOUT for proper
operation. An external bus arbitration circuit asserts BG when the
DSP56303 becomes the next bus master. When BG is asserted, the
DSP56303 must wait until BB is deasserted before taking bus mastership.
When BG is deasserted, bus mastership is typically given up at the end of
the current bus cycle. This may occur in the middle of an instruction that
requires more than one external bus cycle for execution.
Bus Busy
Indicates that the bus is active and must be asserted and deasserted
synchronous to CLKOUT. Only after BB is deasserted can the pending
bus master become the bus master (and then assert the signal again).
The bus master can keep BB asserted after ceasing bus activity,
regardless of whether BR is asserted or deasserted. This is called “bus
parking” and allows the current bus master to reuse the bus without
re-arbitration until another device requires the bus. BB is deasserted by
an “active pull-up” method (that is, BB is driven high and then released
and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
Column Address Strobe
When the DSP is the bus master, DRAM uses CAS to strobe the column
address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM
Control Register is cleared, the signal is tri-stated.
Bus Clock
When the DSP is the bus master, BCLK is active when the OMR[ATE] is
set. When BCLK is active and synchronized to CLKOUT by the internal
PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.
Bus Clock Not
When the DSP is the bus master, BCLK is the inverse of the BCLK signal.
Otherwise, the signal is tri-stated.
Signal Description
Interrupt and Mode Control
BR
to be
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