DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 7

• Manufacturer Part Number: DSP56001FE33
• Description: 24-Bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

DSP56001 Electrical Characteristics
Power and Ground Connections
The Vcc power supply should be bypassed to ground using at least four 0.1 uF by- pass capacitors located either underneath the chip
or as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip
Vcc and Gnd should be kept to less than 1/2" per capacitor lead. A four-layer board is recommended, employing two inner layers as
Vcc and Gnd planes. All output pins on the DSP56001 have fast rise and fall times — typically less than 3 ns. with a 10 pf. load. Printed
circuit (PC) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast
output switching times. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB,
and HEN pins. Maximum PC trace lengths on the order of 6" are recommended. Capacitance calculations should consider all device
loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents in the Vcc and GND circuits. Pull up/down
all unused inputs or signals that will be inputs during reset.
Signal Stability
When designing hardware to interface with the Host Interface, it is important to ensure that all signals be clean and free from noise.
Particular attention should be given to the quality of the Host Enable (HEN). All inputs to the port should be stable when HEN is
asserted and should remain stable until HEN has fully returned to the deasserted state. It is important to note that such phenomena
.
as ground-bounce and cross-talk can inadvertently cause HEN to temporarily rise above V
Should this occur without completing
il max
the full logic transition to V
, the DSP56001 Host Port may not correctly update the port status information which can result in
ih min
storing two or more copies of a single down loaded data word. Of course, if a full logic transition occurs, the part will complete a normal
data transfer operation.
DSP56001
MOTOROLA
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