KAD5512P-50_09 INTERSIL [Intersil Corporation], KAD5512P-50_09 Datasheet - Page 21

• Manufacturer Part Number: KAD5512P-50_09
• Description: 12-Bit, 500MSPS A/D Converter
• Manufacturer: INTERSIL [Intersil Corporation]

Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 80h.
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine
the synchronization of the incoming and divided clock
phases. This is particularly important when multiple ADCs
are used in a time-interleaved system. The phase slip
feature allows the rising edge of the divided clock to be
advanced by one input clock cycle when in CLK/2 mode, as
shown in Figure 38. Execution of a phase_slip command is
accomplished by first writing a ‘0’ to bit 0 at address 71h
followed by writing a ‘1’ to bit 0 at address 71h (32 sclk
cycles).
ADC0 CLOCK
ADC1 CLOCK
ADC0 CLOCK
ADC1 CLOCK
ADC0 CLOCK
ADC1 CLOCK
FIGURE 38. PHASE SLIP: CLK÷2 MODE, f
SLIP TWICE
SLIP TWICE
SLIP ONCE
SLIP ONCE
CLK÷2
–Full Scale (0x08)
+Full Scale (0x07)
Nominal Step Size
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
CLK
Mid–Scale (0x00)
PARAMETER
Steps
CLK = CLKP – CLKN
2.00ns
1.00ns
21
DIFFERENTIAL SKEW
4.00ns
0x70[7:0]
CLOCK
+6.5ps
-6.5ps
0.0ps
51fs
256
= 1000MHz
KAD5512P-50
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P-50 has a selectable clock divider that can be
set to divide by two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input”
on page 15). This functionality can be overridden and
controlled through the SPI, as shown in Table 12. This
register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P-50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive strength
in LVDS mode can be set high (3mA) or low (2mA). By
default, the tri-level OUTMODE pin selects the mode and
drive level (refer to “Digital Outputs” on page 16). This
functionality can be overridden and controlled through the
SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 17). This functionality can be overridden
and controlled through the SPI, as shown in Table 14.
This register is not changed by a Soft Reset.
TABLE 12. CLOCK DIVIDER SELECTION
TABLE 14. OUTPUT FORMAT CONTROL
VALUE
VALUE
TABLE 13. OUTPUT MODE CONTROL
VALUE
000
001
010
100
000
001
010
100
000
001
010
100
OUTPUT FORMAT
Two’s Complement
CLOCK DIVIDER
OUTPUT MODE
Offset Binary
Not Allowed
Pin Control
Divide by 1
Divide by 2
Pin Control
Gray Code
0x72[2:0]
0x93[2:0]
Pin Control
LVDS 2mA
LVDS 3mA
0x93[7:5]
LVCMOS
January 16, 2009
FN6805.0